tree 2946732ea71f0826d0330b427a02d8bf05d09865
parent 88679a29120651f2a3ca252ee3c8f79590273e15
author Bartosz Golaszewski <bgolaszewski@baylibre.com> 1480590463 +0100
committer Tom Rini <trini@konsulko.com> 1480953882 -0500

davinci: omapl138_lcdk: increase PLL0 frequency

The LCDC controller on the lcdk board has high memory throughput
requirements. Even with the kernel-side tweaks to master peripheral
and peripheral bus burst priorities, the default PLL0 frquency of
300 MHz is not enough to service the LCD controller and causes
DMA FIFO underflows.

Increment the PLL0 multiplier to 37, resulting in PLL0 frequency of
456 MHz - the same value that downstream reference u-boot from Texas
Instruments uses.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>