diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 81fe600..f7a8891 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,6 +9,7 @@
 obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
+obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
 obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
 obj-$(CONFIG_CLK_EXYNOS) += exynos/
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index b483c1e..6e4d672 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -1,91 +1,78 @@
 /*
  * Copyright (C) 2015 Google, Inc
  * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2016, NVIDIA CORPORATION.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
 #include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <dm/lists.h>
-#include <dm/root.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-ulong clk_get_rate(struct udevice *dev)
+static inline struct clk_ops *clk_dev_ops(struct udevice *dev)
 {
-	struct clk_ops *ops = clk_get_ops(dev);
-
-	if (!ops->get_rate)
-		return -ENOSYS;
-
-	return ops->get_rate(dev);
-}
-
-ulong clk_set_rate(struct udevice *dev, ulong rate)
-{
-	struct clk_ops *ops = clk_get_ops(dev);
-
-	if (!ops->set_rate)
-		return -ENOSYS;
-
-	return ops->set_rate(dev, rate);
-}
-
-int clk_enable(struct udevice *dev, int periph)
-{
-	struct clk_ops *ops = clk_get_ops(dev);
-
-	if (!ops->enable)
-		return -ENOSYS;
-
-	return ops->enable(dev, periph);
-}
-
-ulong clk_get_periph_rate(struct udevice *dev, int periph)
-{
-	struct clk_ops *ops = clk_get_ops(dev);
-
-	if (!ops->get_periph_rate)
-		return -ENOSYS;
-
-	return ops->get_periph_rate(dev, periph);
-}
-
-ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
-{
-	struct clk_ops *ops = clk_get_ops(dev);
-
-	if (!ops->set_periph_rate)
-		return -ENOSYS;
-
-	return ops->set_periph_rate(dev, periph, rate);
+	return (struct clk_ops *)dev->driver->ops;
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL)
-int clk_get_by_index(struct udevice *dev, int index, struct udevice **clk_devp)
+#ifdef CONFIG_SPL_BUILD
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 {
 	int ret;
-#ifdef CONFIG_SPL_BUILD
 	u32 cell[2];
 
 	if (index != 0)
 		return -ENOSYS;
-	assert(*clk_devp);
-	ret = uclass_get_device(UCLASS_CLK, 0, clk_devp);
+	assert(clk);
+	ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
 	if (ret)
 		return ret;
 	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks",
 				   cell, 2);
 	if (ret)
 		return ret;
-	return cell[1];
-#else
-	struct fdtdec_phandle_args args;
+	clk->id = cell[1];
+	return 0;
+}
 
-	assert(*clk_devp);
+int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
+{
+	return -ENOSYS;
+}
+#else
+static int clk_of_xlate_default(struct clk *clk,
+				struct fdtdec_phandle_args *args)
+{
+	debug("%s(clk=%p)\n", __func__, clk);
+
+	if (args->args_count > 1) {
+		debug("Invaild args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	if (args->args_count)
+		clk->id = args->args[0];
+	else
+		clk->id = 0;
+
+	return 0;
+}
+
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
+{
+	int ret;
+	struct fdtdec_phandle_args args;
+	struct udevice *dev_clk;
+	struct clk_ops *ops;
+
+	debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
+
+	assert(clk);
 	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
 					     "clocks", "#clock-cells", 0, index,
 					     &args);
@@ -95,16 +82,117 @@
 		return ret;
 	}
 
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, clk_devp);
+	ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev_clk);
 	if (ret) {
 		debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
 		      __func__, ret);
 		return ret;
 	}
-	return args.args_count > 0 ? args.args[0] : 0;
-#endif
+	ops = clk_dev_ops(dev_clk);
+
+	if (ops->of_xlate)
+		ret = ops->of_xlate(clk, &args);
+	else
+		ret = clk_of_xlate_default(clk, &args);
+	if (ret) {
+		debug("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	return clk_request(dev_clk, clk);
+}
+
+int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
+
+	index = fdt_find_string(gd->fdt_blob, dev->of_offset, "clock-names",
+				name);
+	if (index < 0) {
+		debug("fdt_find_string() failed: %d\n", index);
+		return index;
+	}
+
+	return clk_get_by_index(dev, index, clk);
 }
 #endif
+#endif
+
+int clk_request(struct udevice *dev, struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(dev);
+
+	debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
+
+	clk->dev = dev;
+
+	if (!ops->request)
+		return 0;
+
+	return ops->request(clk);
+}
+
+int clk_free(struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p)\n", __func__, clk);
+
+	if (!ops->free)
+		return 0;
+
+	return ops->free(clk);
+}
+
+ulong clk_get_rate(struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p)\n", __func__, clk);
+
+	if (!ops->get_rate)
+		return -ENOSYS;
+
+	return ops->get_rate(clk);
+}
+
+ulong clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
+
+	if (!ops->set_rate)
+		return -ENOSYS;
+
+	return ops->set_rate(clk, rate);
+}
+
+int clk_enable(struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p)\n", __func__, clk);
+
+	if (!ops->enable)
+		return -ENOSYS;
+
+	return ops->enable(clk);
+}
+
+int clk_disable(struct clk *clk)
+{
+	struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+	debug("%s(clk=%p)\n", __func__, clk);
+
+	if (!ops->disable)
+		return -ENOSYS;
+
+	return ops->disable(clk);
+}
 
 UCLASS_DRIVER(clk) = {
 	.id		= UCLASS_CLK,
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 8beda9c..797e537 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm/device.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -16,19 +16,16 @@
 
 #define to_clk_fixed_rate(dev)	((struct clk_fixed_rate *)dev_get_platdata(dev))
 
-static ulong clk_fixed_rate_get_rate(struct udevice *dev)
+static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
-	return to_clk_fixed_rate(dev)->fixed_rate;
-}
+	if (clk->id != 0)
+		return -EINVAL;
 
-static ulong clk_fixed_rate_get_periph_rate(struct udevice *dev, int periph)
-{
-	return clk_fixed_rate_get_rate(dev);
+	return to_clk_fixed_rate(clk->dev)->fixed_rate;
 }
 
 const struct clk_ops clk_fixed_rate_ops = {
 	.get_rate = clk_fixed_rate_get_rate,
-	.get_periph_rate = clk_fixed_rate_get_periph_rate,
 };
 
 static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
diff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c
index 5d88354..70ec354 100644
--- a/drivers/clk/clk_pic32.c
+++ b/drivers/clk/clk_pic32.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <div64.h>
 #include <wait_bit.h>
@@ -339,24 +339,17 @@
 	pic32_mpll_init(priv);
 }
 
-static ulong pic32_clk_get_rate(struct udevice *dev)
+static ulong pic32_get_rate(struct clk *clk)
 {
-	struct pic32_clk_priv *priv = dev_get_priv(dev);
-
-	return pic32_get_cpuclk(priv);
-}
-
-static ulong pic32_get_periph_rate(struct udevice *dev, int periph)
-{
-	struct pic32_clk_priv *priv = dev_get_priv(dev);
+	struct pic32_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong rate;
 
-	switch (periph) {
+	switch (clk->id) {
 	case PB1CLK ... PB7CLK:
-		rate = pic32_get_pbclk(priv, periph);
+		rate = pic32_get_pbclk(priv, clk->id);
 		break;
 	case REF1CLK ... REF5CLK:
-		rate = pic32_get_refclk(priv, periph);
+		rate = pic32_get_refclk(priv, clk->id);
 		break;
 	case PLLCLK:
 		rate = pic32_get_pll_rate(priv);
@@ -372,15 +365,15 @@
 	return rate;
 }
 
-static ulong pic32_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong pic32_set_rate(struct clk *clk, ulong rate)
 {
-	struct pic32_clk_priv *priv = dev_get_priv(dev);
+	struct pic32_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong pll_hz;
 
-	switch (periph) {
+	switch (clk->id) {
 	case REF1CLK ... REF5CLK:
 		pll_hz = pic32_get_pll_rate(priv);
-		pic32_set_refclk(priv, periph, pll_hz, rate, ROCLK_SRC_SPLL);
+		pic32_set_refclk(priv, clk->id, pll_hz, rate, ROCLK_SRC_SPLL);
 		break;
 	default:
 		break;
@@ -390,9 +383,8 @@
 }
 
 static struct clk_ops pic32_pic32_clk_ops = {
-	.get_rate = pic32_clk_get_rate,
-	.set_periph_rate = pic32_set_periph_rate,
-	.get_periph_rate = pic32_get_periph_rate,
+	.set_rate = pic32_set_rate,
+	.get_rate = pic32_get_rate,
 };
 
 static int pic32_clk_probe(struct udevice *dev)
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index 7ec65bd..6202c9d 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
 #include <syscon.h>
@@ -18,10 +18,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct rk3036_clk_plat {
-	enum rk_clk_id clk_id;
-};
-
 struct rk3036_clk_priv {
 	struct rk3036_cru *cru;
 	ulong rate;
@@ -315,31 +311,30 @@
 	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
 }
 
-static ulong rk3036_clk_get_rate(struct udevice *dev)
+static ulong rk3036_clk_get_rate(struct clk *clk)
 {
-	struct rk3036_clk_plat *plat = dev_get_platdata(dev);
-	struct rk3036_clk_priv *priv = dev_get_priv(dev);
+	struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
 
-	debug("%s\n", dev->name);
-	return rkclk_pll_get_rate(priv->cru, plat->clk_id);
+	switch (clk->id) {
+	case 0 ... 63:
+		return rkclk_pll_get_rate(priv->cru, clk->id);
+	default:
+		return -ENOENT;
+	}
 }
 
-static ulong rk3036_clk_set_rate(struct udevice *dev, ulong rate)
+static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
 {
-	debug("%s\n", dev->name);
+	struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong new_rate, gclk_rate;
 
-	return 0;
-}
-
-static ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate)
-{
-	struct rk3036_clk_priv *priv = dev_get_priv(dev);
-	ulong new_rate;
-
-	switch (periph) {
+	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case 0 ... 63:
+		return 0;
 	case HCLK_EMMC:
-		new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev),
-						periph, rate);
+		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
+						clk->id, rate);
 		break;
 	default:
 		return -ENOENT;
@@ -351,60 +346,21 @@
 static struct clk_ops rk3036_clk_ops = {
 	.get_rate	= rk3036_clk_get_rate,
 	.set_rate	= rk3036_clk_set_rate,
-	.set_periph_rate = rk3036_set_periph_rate,
 };
 
 static int rk3036_clk_probe(struct udevice *dev)
 {
-	struct rk3036_clk_plat *plat = dev_get_platdata(dev);
 	struct rk3036_clk_priv *priv = dev_get_priv(dev);
 
-	if (plat->clk_id != CLK_OSC) {
-		struct rk3036_clk_priv *parent_priv = dev_get_priv(dev->parent);
-
-		priv->cru = parent_priv->cru;
-		return 0;
-	}
 	priv->cru = (struct rk3036_cru *)dev_get_addr(dev);
 	rkclk_init(priv->cru);
 
 	return 0;
 }
 
-static const char *const clk_name[] = {
-	"osc",
-	"apll",
-	"dpll",
-	"cpll",
-	"gpll",
-	"mpll",
-};
-
 static int rk3036_clk_bind(struct udevice *dev)
 {
-	struct rk3036_clk_plat *plat = dev_get_platdata(dev);
-	int pll, ret;
-
-	/* We only need to set up the root clock */
-	if (dev->of_offset == -1) {
-		plat->clk_id = CLK_OSC;
-		return 0;
-	}
-
-	/* Create devices for P main clocks */
-	for (pll = 1; pll < CLK_COUNT; pll++) {
-		struct udevice *child;
-		struct rk3036_clk_plat *cplat;
-
-		debug("%s %s\n", __func__, clk_name[pll]);
-		ret = device_bind_driver(dev, "clk_rk3036", clk_name[pll],
-					 &child);
-		if (ret)
-			return ret;
-
-		cplat = dev_get_platdata(child);
-		cplat->clk_id = pll;
-	}
+	int ret;
 
 	/* The reset driver does not have a device node, so bind it here */
 	ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev);
@@ -424,7 +380,6 @@
 	.id		= UCLASS_CLK,
 	.of_match	= rk3036_clk_ids,
 	.priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
-	.platdata_auto_alloc_size = sizeof(struct rk3036_clk_plat),
 	.ops		= &rk3036_clk_ops,
 	.bind		= rk3036_clk_bind,
 	.probe		= rk3036_clk_probe,
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index d88893c..2285453 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -5,7 +5,7 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
 #include <syscon.h>
@@ -21,10 +21,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct rk3288_clk_plat {
-	enum rk_clk_id clk_id;
-};
-
 struct rk3288_clk_priv {
 	struct rk3288_grf *grf;
 	struct rk3288_cru *cru;
@@ -135,34 +131,18 @@
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 
-int rkclk_get_clk(enum rk_clk_id clk_id, struct udevice **devp)
-{
-	struct udevice *dev;
-
-	for (uclass_find_first_device(UCLASS_CLK, &dev);
-	     dev;
-	     uclass_find_next_device(&dev)) {
-		struct rk3288_clk_plat *plat = dev_get_platdata(dev);
-
-		if (plat->clk_id == clk_id) {
-			*devp = dev;
-			return device_probe(dev);
-		}
-	}
-
-	return -ENODEV;
-}
-
 void *rockchip_get_cru(void)
 {
 	struct rk3288_clk_priv *priv;
 	struct udevice *dev;
 	int ret;
 
-	ret = rkclk_get_clk(CLK_GENERAL, &dev);
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev);
 	if (ret)
 		return ERR_PTR(ret);
+
 	priv = dev_get_priv(dev);
+
 	return priv->cru;
 }
 
@@ -539,32 +519,6 @@
 	}
 }
 
-static ulong rk3288_clk_get_rate(struct udevice *dev)
-{
-	struct rk3288_clk_plat *plat = dev_get_platdata(dev);
-	struct rk3288_clk_priv *priv = dev_get_priv(dev);
-
-	debug("%s\n", dev->name);
-	return rkclk_pll_get_rate(priv->cru, plat->clk_id);
-}
-
-static ulong rk3288_clk_set_rate(struct udevice *dev, ulong rate)
-{
-	struct rk3288_clk_plat *plat = dev_get_platdata(dev);
-	struct rk3288_clk_priv *priv = dev_get_priv(dev);
-
-	debug("%s\n", dev->name);
-	switch (plat->clk_id) {
-	case CLK_DDR:
-		rkclk_configure_ddr(priv->cru, priv->grf, rate);
-		break;
-	default:
-		return -ENOENT;
-	}
-
-	return 0;
-}
-
 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
 				  int periph)
 {
@@ -710,27 +664,25 @@
 	return rockchip_spi_get_clk(cru, gclk_rate, periph);
 }
 
-static ulong rk3288_get_periph_rate(struct udevice *dev, int periph)
+static ulong rk3288_clk_get_rate(struct clk *clk)
 {
-	struct rk3288_clk_priv *priv = dev_get_priv(dev);
-	struct udevice *gclk;
+	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong new_rate, gclk_rate;
-	int ret;
 
-	ret = rkclk_get_clk(CLK_GENERAL, &gclk);
-	if (ret)
-		return ret;
-	gclk_rate = clk_get_rate(gclk);
-	switch (periph) {
+	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case 0 ... 63:
+		new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
+		break;
 	case HCLK_EMMC:
 	case HCLK_SDMMC:
 	case HCLK_SDIO0:
-		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, periph);
+		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
 		break;
 	case SCLK_SPI0:
 	case SCLK_SPI1:
 	case SCLK_SPI2:
-		new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, periph);
+		new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
 		break;
 	case PCLK_I2C0:
 	case PCLK_I2C1:
@@ -746,36 +698,34 @@
 	return new_rate;
 }
 
-static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct rk3288_clk_priv *priv = dev_get_priv(dev);
+	struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
 	struct rk3288_cru *cru = priv->cru;
-	struct udevice *gclk;
 	ulong new_rate, gclk_rate;
-	int ret;
 
-	ret = rkclk_get_clk(CLK_GENERAL, &gclk);
-	if (ret)
-		return ret;
-	gclk_rate = clk_get_rate(gclk);
-	switch (periph) {
+	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+	switch (clk->id) {
+	case CLK_DDR:
+		new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
+		break;
 	case HCLK_EMMC:
 	case HCLK_SDMMC:
 	case HCLK_SDIO0:
-		new_rate = rockchip_mmc_set_clk(cru, gclk_rate, periph, rate);
+		new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
 		break;
 	case SCLK_SPI0:
 	case SCLK_SPI1:
 	case SCLK_SPI2:
-		new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
+		new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
 		break;
 #ifndef CONFIG_SPL_BUILD
 	case SCLK_MAC:
-		new_rate = rockchip_mac_set_clk(priv->cru, periph, rate);
+		new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
 		break;
 	case DCLK_VOP0:
 	case DCLK_VOP1:
-		new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
+		new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
 		break;
 	case SCLK_EDP_24M:
 		/* clk_edp_24M source: 24M */
@@ -795,7 +745,7 @@
 		div = CPLL_HZ / rate;
 		assert((div - 1 < 64) && (div * rate == CPLL_HZ));
 
-		switch (periph) {
+		switch (clk->id) {
 		case ACLK_VOP0:
 			rk_clrsetreg(&cru->cru_clksel_con[31],
 				     3 << 6 | 0x1f << 0,
@@ -831,22 +781,12 @@
 static struct clk_ops rk3288_clk_ops = {
 	.get_rate	= rk3288_clk_get_rate,
 	.set_rate	= rk3288_clk_set_rate,
-	.set_periph_rate = rk3288_set_periph_rate,
-	.get_periph_rate = rk3288_get_periph_rate,
 };
 
 static int rk3288_clk_probe(struct udevice *dev)
 {
-	struct rk3288_clk_plat *plat = dev_get_platdata(dev);
 	struct rk3288_clk_priv *priv = dev_get_priv(dev);
 
-	if (plat->clk_id != CLK_OSC) {
-		struct rk3288_clk_priv *parent_priv = dev_get_priv(dev->parent);
-
-		priv->cru = parent_priv->cru;
-		priv->grf = parent_priv->grf;
-		return 0;
-	}
 	priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 #ifdef CONFIG_SPL_BUILD
@@ -856,39 +796,9 @@
 	return 0;
 }
 
-static const char *const clk_name[CLK_COUNT] = {
-	"osc",
-	"apll",
-	"dpll",
-	"cpll",
-	"gpll",
-	"npll",
-};
-
 static int rk3288_clk_bind(struct udevice *dev)
 {
-	struct rk3288_clk_plat *plat = dev_get_platdata(dev);
-	int pll, ret;
-
-	/* We only need to set up the root clock */
-	if (dev->of_offset == -1) {
-		plat->clk_id = CLK_OSC;
-		return 0;
-	}
-
-	/* Create devices for P main clocks */
-	for (pll = 1; pll < CLK_COUNT; pll++) {
-		struct udevice *child;
-		struct rk3288_clk_plat *cplat;
-
-		debug("%s %s\n", __func__, clk_name[pll]);
-		ret = device_bind_driver(dev, "clk_rk3288", clk_name[pll],
-					 &child);
-		if (ret)
-			return ret;
-		cplat = dev_get_platdata(child);
-		cplat->clk_id = pll;
-	}
+	int ret;
 
 	/* The reset driver does not have a device node, so bind it here */
 	ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
@@ -908,7 +818,6 @@
 	.id		= UCLASS_CLK,
 	.of_match	= rk3288_clk_ids,
 	.priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
-	.platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
 	.ops		= &rk3288_clk_ops,
 	.bind		= rk3288_clk_bind,
 	.probe		= rk3288_clk_probe,
diff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c
index 367130f..c6bd7c6 100644
--- a/drivers/clk/clk_sandbox.c
+++ b/drivers/clk/clk_sandbox.c
@@ -5,61 +5,63 @@
  */
 
 #include <common.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/test.h>
+#include <asm/clk.h>
 
 struct sandbox_clk_priv {
-	ulong rate;
-	ulong periph_rate[PERIPH_ID_COUNT];
+	ulong rate[SANDBOX_CLK_ID_COUNT];
+	bool enabled[SANDBOX_CLK_ID_COUNT];
 };
 
-static ulong sandbox_clk_get_rate(struct udevice *dev)
+static ulong sandbox_clk_get_rate(struct clk *clk)
 {
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
 
-	return priv->rate;
+	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
+
+	return priv->rate[clk->id];
 }
 
-static ulong sandbox_clk_set_rate(struct udevice *dev, ulong rate)
+static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong old_rate;
+
+	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
 
 	if (!rate)
 		return -EINVAL;
-	priv->rate = rate;
-	return 0;
-}
 
-static ulong sandbox_get_periph_rate(struct udevice *dev, int periph)
-{
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
-
-	if (periph < PERIPH_ID_FIRST || periph >= PERIPH_ID_COUNT)
-		return -EINVAL;
-	return priv->periph_rate[periph];
-}
-
-static ulong sandbox_set_periph_rate(struct udevice *dev, int periph,
-				     ulong rate)
-{
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
-	ulong old_rate;
-
-	if (periph < PERIPH_ID_FIRST || periph >= PERIPH_ID_COUNT)
-		return -EINVAL;
-	old_rate = priv->periph_rate[periph];
-	priv->periph_rate[periph] = rate;
+	old_rate = priv->rate[clk->id];
+	priv->rate[clk->id] = rate;
 
 	return old_rate;
 }
 
-static int sandbox_clk_probe(struct udevice *dev)
+static int sandbox_clk_enable(struct clk *clk)
 {
-	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
 
-	priv->rate = SANDBOX_CLK_RATE;
+	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
+
+	priv->enabled[clk->id] = true;
+
+	return 0;
+}
+
+static int sandbox_clk_disable(struct clk *clk)
+{
+	struct sandbox_clk_priv *priv = dev_get_priv(clk->dev);
+
+	if (clk->id < 0 || clk->id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
+
+	priv->enabled[clk->id] = false;
 
 	return 0;
 }
@@ -67,8 +69,8 @@
 static struct clk_ops sandbox_clk_ops = {
 	.get_rate	= sandbox_clk_get_rate,
 	.set_rate	= sandbox_clk_set_rate,
-	.get_periph_rate = sandbox_get_periph_rate,
-	.set_periph_rate = sandbox_set_periph_rate,
+	.enable		= sandbox_clk_enable,
+	.disable	= sandbox_clk_disable,
 };
 
 static const struct udevice_id sandbox_clk_ids[] = {
@@ -82,5 +84,24 @@
 	.of_match	= sandbox_clk_ids,
 	.ops		= &sandbox_clk_ops,
 	.priv_auto_alloc_size = sizeof(struct sandbox_clk_priv),
-	.probe		= sandbox_clk_probe,
 };
+
+ulong sandbox_clk_query_rate(struct udevice *dev, int id)
+{
+	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
+
+	return priv->rate[id];
+}
+
+int sandbox_clk_query_enable(struct udevice *dev, int id)
+{
+	struct sandbox_clk_priv *priv = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_ID_COUNT)
+		return -EINVAL;
+
+	return priv->enabled[id];
+}
diff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c
new file mode 100644
index 0000000..999100d
--- /dev/null
+++ b/drivers/clk/clk_sandbox_test.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <asm/clk.h>
+
+struct sandbox_clk_test {
+	struct clk clks[SANDBOX_CLK_TEST_ID_COUNT];
+};
+
+static const char * const sandbox_clk_test_names[] = {
+	[SANDBOX_CLK_TEST_ID_FIXED] = "fixed",
+	[SANDBOX_CLK_TEST_ID_SPI] = "spi",
+	[SANDBOX_CLK_TEST_ID_I2C] = "i2c",
+};
+
+int sandbox_clk_test_get(struct udevice *dev)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+	int i, ret;
+
+	for (i = 0; i < SANDBOX_CLK_TEST_ID_COUNT; i++) {
+		ret = clk_get_by_name(dev, sandbox_clk_test_names[i],
+				      &sbct->clks[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+ulong sandbox_clk_test_get_rate(struct udevice *dev, int id)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+		return -EINVAL;
+
+	return clk_get_rate(&sbct->clks[id]);
+}
+
+ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+		return -EINVAL;
+
+	return clk_set_rate(&sbct->clks[id], rate);
+}
+
+int sandbox_clk_test_enable(struct udevice *dev, int id)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+		return -EINVAL;
+
+	return clk_enable(&sbct->clks[id]);
+}
+
+int sandbox_clk_test_disable(struct udevice *dev, int id)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+
+	if (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)
+		return -EINVAL;
+
+	return clk_disable(&sbct->clks[id]);
+}
+
+int sandbox_clk_test_free(struct udevice *dev)
+{
+	struct sandbox_clk_test *sbct = dev_get_priv(dev);
+	int i, ret;
+
+	for (i = 0; i < SANDBOX_CLK_TEST_ID_COUNT; i++) {
+		ret = clk_free(&sbct->clks[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id sandbox_clk_test_ids[] = {
+	{ .compatible = "sandbox,clk-test" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_clk_test) = {
+	.name = "sandbox_clk_test",
+	.id = UCLASS_MISC,
+	.of_match = sandbox_clk_test_ids,
+	.priv_auto_alloc_size = sizeof(struct sandbox_clk_test),
+};
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
index bf5d0e6..1f017a3 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -9,7 +9,7 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <asm/io.h>
 #include <dt-bindings/clock/exynos7420-clk.h>
 #include "clk-pll.h"
@@ -67,11 +67,11 @@
 	unsigned long sclk_uart2;
 };
 
-static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
+static ulong exynos7420_topc_get_rate(struct clk *clk)
 {
-	struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+	struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);
 
-	switch (periph) {
+	switch (clk->id) {
 	case DOUT_SCLK_BUS0_PLL:
 	case SCLK_BUS0_PLL_A:
 	case SCLK_BUS0_PLL_B:
@@ -86,14 +86,14 @@
 }
 
 static struct clk_ops exynos7420_clk_topc_ops = {
-	.get_periph_rate	= exynos7420_topc_get_periph_rate,
+	.get_rate	= exynos7420_topc_get_rate,
 };
 
 static int exynos7420_clk_topc_probe(struct udevice *dev)
 {
 	struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
 	struct exynos7420_clk_cmu_topc *topc;
-	struct udevice *clk_dev;
+	struct clk in_clk;
 	unsigned long rate;
 	fdt_addr_t base;
 	int ret;
@@ -105,9 +105,9 @@
 	topc = (struct exynos7420_clk_cmu_topc *)base;
 	priv->topc = topc;
 
-	ret = clk_get_by_index(dev, 0, &clk_dev);
+	ret = clk_get_by_index(dev, 0, &in_clk);
 	if (ret >= 0)
-		priv->fin_freq = clk_get_rate(clk_dev);
+		priv->fin_freq = clk_get_rate(&in_clk);
 
 	rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
 	if (readl(&topc->mux_sel[1]) & (1 << 16))
@@ -122,12 +122,12 @@
 	return 0;
 }
 
-static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
+static ulong exynos7420_top0_get_rate(struct clk *clk)
 {
-	struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
+	struct exynos7420_clk_top0_priv *priv = dev_get_priv(clk->dev);
 	struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
 
-	switch (periph) {
+	switch (clk->id) {
 	case CLK_SCLK_UART2:
 		return priv->mout_top0_bus0_pll_half /
 			DIVIDER(&top0->div_peric[3], 8, 0xf);
@@ -137,14 +137,14 @@
 }
 
 static struct clk_ops exynos7420_clk_top0_ops = {
-	.get_periph_rate	= exynos7420_top0_get_periph_rate,
+	.get_rate	= exynos7420_top0_get_rate,
 };
 
 static int exynos7420_clk_top0_probe(struct udevice *dev)
 {
 	struct exynos7420_clk_top0_priv *priv;
 	struct exynos7420_clk_cmu_top0 *top0;
-	struct udevice *clk_dev;
+	struct clk in_clk;
 	fdt_addr_t base;
 	int ret;
 
@@ -159,10 +159,10 @@
 	top0 = (struct exynos7420_clk_cmu_top0 *)base;
 	priv->top0 = top0;
 
-	ret = clk_get_by_index(dev, 1, &clk_dev);
+	ret = clk_get_by_index(dev, 1, &in_clk);
 	if (ret >= 0) {
 		priv->mout_top0_bus0_pll_half =
-			clk_get_periph_rate(clk_dev, ret);
+			clk_get_rate(&in_clk);
 		if (readl(&top0->mux_sel[1]) & (1 << 16))
 			priv->mout_top0_bus0_pll_half >>= 1;
 	}
@@ -170,18 +170,18 @@
 	return 0;
 }
 
-static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
+static ulong exynos7420_peric1_get_rate(struct clk *clk)
 {
-	struct udevice *clk_dev;
+	struct clk in_clk;
 	unsigned int ret;
 	unsigned long freq = 0;
 
-	switch (periph) {
+	switch (clk->id) {
 	case SCLK_UART2:
-		ret = clk_get_by_index(dev, 3, &clk_dev);
+		ret = clk_get_by_index(clk->dev, 3, &in_clk);
 		if (ret < 0)
 			return ret;
-		freq = clk_get_periph_rate(clk_dev, ret);
+		freq = clk_get_rate(&in_clk);
 		break;
 	}
 
@@ -189,7 +189,7 @@
 }
 
 static struct clk_ops exynos7420_clk_peric1_ops = {
-	.get_periph_rate	= exynos7420_peric1_get_periph_rate,
+	.get_rate	= exynos7420_peric1_get_rate,
 };
 
 static const struct udevice_id exynos7420_clk_topc_compat[] = {
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 25c163b..2f5d4d8 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -9,14 +9,14 @@
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
-#include <clk.h>
+#include <clk-uclass.h>
 #include <dm/device.h>
 
 #include "clk-uniphier.h"
 
-static int uniphier_clk_enable(struct udevice *dev, int index)
+static int uniphier_clk_enable(struct clk *clk)
 {
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
 	struct uniphier_clk_gate_data *gate = priv->socdata->gate;
 	unsigned int nr_gate = priv->socdata->nr_gate;
 	void __iomem *reg;
@@ -24,7 +24,7 @@
 	int i;
 
 	for (i = 0; i < nr_gate; i++) {
-		if (gate[i].index != index)
+		if (gate[i].index != clk->id)
 			continue;
 
 		reg = priv->base + gate[i].reg;
@@ -41,9 +41,9 @@
 	return 0;
 }
 
-static ulong uniphier_clk_get_rate(struct udevice *dev, int index)
+static ulong uniphier_clk_get_rate(struct clk *clk)
 {
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
 	struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
 	unsigned int nr_rdata = priv->socdata->nr_rate;
 	void __iomem *reg;
@@ -52,7 +52,7 @@
 	int i;
 
 	for (i = 0; i < nr_rdata; i++) {
-		if (rdata[i].index != index)
+		if (rdata[i].index != clk->id)
 			continue;
 
 		if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
@@ -75,9 +75,9 @@
 	return matched_rate;
 }
 
-static ulong uniphier_clk_set_rate(struct udevice *dev, int index, ulong rate)
+static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct uniphier_clk_priv *priv = dev_get_priv(dev);
+	struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
 	struct uniphier_clk_rate_data *rdata = priv->socdata->rate;
 	unsigned int nr_rdata = priv->socdata->nr_rate;
 	void __iomem *reg;
@@ -87,7 +87,7 @@
 
 	/* first, decide the best match rate */
 	for (i = 0; i < nr_rdata; i++) {
-		if (rdata[i].index != index)
+		if (rdata[i].index != clk->id)
 			continue;
 
 		if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED)
@@ -105,7 +105,7 @@
 
 	/* second, really set registers */
 	for (i = 0; i < nr_rdata; i++) {
-		if (rdata[i].index != index || rdata[i].rate != best_rate)
+		if (rdata[i].index != clk->id || rdata[i].rate != best_rate)
 			continue;
 
 		reg = priv->base + rdata[i].reg;
@@ -124,8 +124,8 @@
 
 const struct clk_ops uniphier_clk_ops = {
 	.enable = uniphier_clk_enable,
-	.get_periph_rate = uniphier_clk_get_rate,
-	.set_periph_rate = uniphier_clk_set_rate,
+	.get_rate = uniphier_clk_get_rate,
+	.set_rate = uniphier_clk_set_rate,
 };
 
 int uniphier_clk_probe(struct udevice *dev)
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index c6ecd11..2dd3fc0 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <clk.h>
 #include <dm/device.h>
 
 #include "clk-uniphier.h"
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
index 3fceade..63b1418 100644
--- a/drivers/i2c/rk_i2c.c
+++ b/drivers/i2c/rk_i2c.c
@@ -29,10 +29,9 @@
 #define RK_I2C_FIFO_SIZE	32
 
 struct rk_i2c {
-	struct udevice *clk;
+	struct clk clk;
 	struct i2c_regs *regs;
 	unsigned int speed;
-	int clk_id;
 };
 
 static inline void rk_i2c_get_div(int div, int *divh, int *divl)
@@ -55,7 +54,7 @@
 	int div, divl, divh;
 
 	/* First get i2c rate from pclk */
-	i2c_rate = clk_get_periph_rate(i2c->clk, i2c->clk_id);
+	i2c_rate = clk_get_rate(&i2c->clk);
 
 	div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
 	divh = 0;
@@ -362,7 +361,6 @@
 		      bus->name, ret);
 		return ret;
 	}
-	priv->clk_id = ret;
 
 	return 0;
 }
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index 1e2a29b..64bbf0c 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -49,7 +49,8 @@
 					"clock-frequency", 400000);
 	uint clkd[2]; /* clk_id and clk_no */
 	int clk_offset;
-	struct udevice *clk;
+	struct udevice *clk_dev;
+	struct clk clk;
 	int ret;
 
 	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
@@ -61,11 +62,17 @@
 	if (clk_offset < 0)
 		return clk_offset;
 
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk);
+	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
 	if (ret)
 		return ret;
 
-	ret = clk_set_periph_rate(clk, clkd[1], clk_rate);
+	clk.id = clkd[1];
+	ret = clk_request(clk_dev, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_set_rate(&clk, clk_rate);
+	clk_free(&clk);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 750ab9f..d41d60c 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -24,8 +24,7 @@
 };
 
 struct rockchip_dwmmc_priv {
-	struct udevice *clk;
-	int periph;
+	struct clk clk;
 	struct dwmci_host host;
 };
 
@@ -35,7 +34,7 @@
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = clk_set_periph_rate(priv->clk, priv->periph, freq);
+	ret = clk_set_rate(&priv->clk, freq);
 	if (ret < 0) {
 		debug("%s: err=%d\n", __func__, ret);
 		return ret;
@@ -81,7 +80,6 @@
 	ret = clk_get_by_index(dev, 0, &priv->clk);
 	if (ret < 0)
 		return ret;
-	priv->periph = ret;
 
 	if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
 				 "clock-freq-min-max", minmax, 2))
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 4978cca..152e987 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -651,8 +651,7 @@
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	fdt_addr_t base;
-	struct udevice *clk_dev;
-	int clk_id;
+	struct clk clk;
 	int ret;
 
 	priv->dev = dev;
@@ -665,20 +664,22 @@
 	if (!priv->regbase)
 		return -ENOMEM;
 
-	clk_id = clk_get_by_index(dev, 0, &clk_dev);
-	if (clk_id < 0) {
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret < 0) {
 		dev_err(dev, "failed to get host clock\n");
-		return clk_id;
+		return ret;
 	}
 
 	/* set to max rate */
-	priv->mclk = clk_set_periph_rate(clk_dev, clk_id, ULONG_MAX);
+	priv->mclk = clk_set_rate(&clk, ULONG_MAX);
 	if (IS_ERR_VALUE(priv->mclk)) {
 		dev_err(dev, "failed to set rate for host clock\n");
+		clk_free(&clk);
 		return priv->mclk;
 	}
 
-	ret = clk_enable(clk_dev, clk_id);
+	ret = clk_enable(&clk);
+	clk_free(&clk);
 	if (ret) {
 		dev_err(dev, "failed to enable host clock\n");
 		return ret;
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 80fb89e..a7cab13 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -150,7 +150,8 @@
 					"clock-frequency", 115200);
 	uint clkd[2]; /* clk_id and clk_no */
 	int clk_offset;
-	struct udevice *clk;
+	struct udevice *clk_dev;
+	struct clk clk;
 	int ret;
 
 	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
@@ -162,11 +163,17 @@
 	if (clk_offset < 0)
 		return clk_offset;
 
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk);
+	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
 	if (ret)
 		return ret;
 
-	ret = clk_set_periph_rate(clk, clkd[1], clk_rate);
+	clk.id = clkd[1];
+	ret = clk_request(clk_dev, &clk);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_set_rate(&clk, clk_rate);
+	clk_free(&clk);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c
index af9fbbf..c2141f0 100644
--- a/drivers/serial/serial_pic32.c
+++ b/drivers/serial/serial_pic32.c
@@ -135,7 +135,7 @@
 static int pic32_uart_probe(struct udevice *dev)
 {
 	struct pic32_uart_priv *priv = dev_get_priv(dev);
-	struct udevice *clkdev;
+	struct clk clk;
 	fdt_addr_t addr;
 	fdt_size_t size;
 	int ret;
@@ -148,10 +148,11 @@
 	priv->base = ioremap(addr, size);
 
 	/* get clock rate */
-	ret = clk_get_by_index(dev, 0, &clkdev);
+	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0)
 		return ret;
-	priv->uartclk = clk_get_periph_rate(clkdev, ret);
+	priv->uartclk = clk_get_rate(&clk);
+	clk_free(&clk);
 
 	/* initialize serial */
 	return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index cb55c5a..6225479 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -94,13 +94,13 @@
 	u32 uclk;
 
 #ifdef CONFIG_CLK_EXYNOS
-	struct udevice *clk_dev;
+	struct clk clk;
 	u32 ret;
 
-	ret = clk_get_by_index(dev, 1, &clk_dev);
+	ret = clk_get_by_index(dev, 1, &clk);
 	if (ret < 0)
 		return ret;
-	uclk = clk_get_periph_rate(clk_dev, ret);
+	uclk = clk_get_rate(&clk);
 #else
 	uclk = get_uart_clk(plat->port_id);
 #endif
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 9eff423..bc6dfd8 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -35,8 +35,7 @@
 
 struct rockchip_spi_priv {
 	struct rockchip_spi *regs;
-	struct udevice *clk;
-	int clk_id;
+	struct clk clk;
 	unsigned int max_freq;
 	unsigned int mode;
 	ulong last_transaction_us;	/* Time of last transaction end */
@@ -144,7 +143,6 @@
 		      bus->name, ret);
 		return ret;
 	}
-	priv->clk_id = ret;
 
 	plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
 					 50000000);
@@ -175,7 +173,7 @@
 	 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
 	 * is the assumed speed for CLK_GENERAL.
 	 */
-	ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
+	ret = clk_set_rate(&priv->clk, 99000000);
 	if (ret < 0) {
 		debug("%s: Failed to set clock: %d\n", __func__, ret);
 		return ret;
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
index 4444988..e0377ca 100644
--- a/drivers/usb/host/ehci-generic.c
+++ b/drivers/usb/host/ehci-generic.c
@@ -26,15 +26,15 @@
 	int i;
 
 	for (i = 0; ; i++) {
-		struct udevice *clk_dev;
-		int clk_id;
+		struct clk clk;
+		int ret;
 
-		clk_id = clk_get_by_index(dev, i, &clk_dev);
-		if (clk_id < 0)
+		ret = clk_get_by_index(dev, i, &clk);
+		if (ret < 0)
 			break;
-		if (clk_enable(clk_dev, clk_id))
-			printf("failed to enable clock (dev=%s, id=%d)\n",
-			       clk_dev->name, clk_id);
+		if (clk_enable(&clk))
+			printf("failed to enable clock %d\n", i);
+		clk_free(&clk);
 	}
 
 	hccr = map_physmem(dev_get_addr(dev), 0x100, MAP_NOCACHE);
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 124ddf6..7ece038 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -1009,8 +1009,7 @@
 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 	struct rk_edp_priv *priv = dev_get_priv(dev);
 	struct rk3288_edp *regs = priv->regs;
-	struct udevice *clk;
-	int periph;
+	struct clk clk;
 	int ret;
 
 	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
@@ -1026,8 +1025,8 @@
 
 	ret = clk_get_by_index(dev, 1, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 0);
+		ret = clk_set_rate(&clk, 0);
+		clk_free(&clk);
 	}
 	if (ret) {
 		debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
@@ -1036,8 +1035,8 @@
 
 	ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 192000000);
+		ret = clk_set_rate(&clk, 192000000);
+		clk_free(&clk);
 	}
 	if (ret < 0) {
 		debug("%s: Failed to set clock in source device '%s': ret=%d\n",
diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c
index 5fcb61a..8dd2c87 100644
--- a/drivers/video/rockchip/rk_hdmi.c
+++ b/drivers/video/rockchip/rk_hdmi.c
@@ -859,15 +859,15 @@
 {
 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 	struct rk_hdmi_priv *priv = dev_get_priv(dev);
-	struct udevice *reg, *clk;
-	int periph;
+	struct udevice *reg;
+	struct clk clk;
 	int ret;
 	int vop_id = uc_plat->source_id;
 
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 0);
+		ret = clk_set_rate(&clk, 0);
+		clk_free(&clk);
 	}
 	if (ret) {
 		debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
@@ -880,8 +880,8 @@
 	 */
 	ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 384000000);
+		ret = clk_set_rate(&clk, 384000000);
+		clk_free(&clk);
 	}
 	if (ret < 0) {
 		debug("%s: Failed to set clock in source device '%s': ret=%d\n",
diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c
index dc10b86..fcbb4d6 100644
--- a/drivers/video/rockchip/rk_lvds.c
+++ b/drivers/video/rockchip/rk_lvds.c
@@ -5,7 +5,6 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <display.h>
 #include <dm.h>
 #include <edid.h>
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index db09d9a..cc26f19 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -195,7 +195,8 @@
 	struct udevice *disp;
 	int ret, remote, i, offset;
 	struct display_plat *disp_uc_plat;
-	struct udevice *clk;
+	struct udevice *dev_clk;
+	struct clk clk;
 
 	vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
 	debug("vop_id=%d\n", vop_id);
@@ -237,11 +238,13 @@
 		return ret;
 	}
 
-	ret = rkclk_get_clk(CLK_NEW, &clk);
+	ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk);
 	if (!ret) {
-		ret = clk_set_periph_rate(clk, DCLK_VOP0 + remote_vop_id,
-					  timing.pixelclock.typ);
+		clk.id = DCLK_VOP0 + remote_vop_id;
+		ret = clk_request(dev_clk, &clk);
 	}
+	if (!ret)
+		ret = clk_set_rate(&clk, timing.pixelclock.typ);
 	if (ret) {
 		debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
 		return ret;