83xx, kmeter1: autodetect size of DDR II RAM
it is possible that some board variants have different DDR II
RAM sizes. So we autodetect the size of the assembled RAM.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
diff --git a/board/keymile/kmeter1/kmeter1.c b/board/keymile/kmeter1/kmeter1.c
index a3c58ae..4f41f1d 100644
--- a/board/keymile/kmeter1/kmeter1.c
+++ b/board/keymile/kmeter1/kmeter1.c
@@ -29,6 +29,8 @@
#include "../common/common.h"
+extern void disable_addr_trans (void);
+extern void enable_addr_trans (void);
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
@@ -111,16 +113,7 @@
u32 ddr_size;
u32 ddr_size_log2;
- msize = CONFIG_SYS_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
- if (ddr_size & 1)
- return -1;
- }
-
- im->sysconf.ddrlaw[0].ar =
- LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-
+ im->sysconf.ddrlaw[0].ar = LAWAR_EN | 0x1e;
im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
@@ -136,6 +129,21 @@
udelay (200);
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+ msize = CONFIG_SYS_DDR_SIZE << 20;
+ disable_addr_trans ();
+ msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+ enable_addr_trans ();
+ msize /= (1024 * 1024);
+ if (CONFIG_SYS_DDR_SIZE != msize) {
+ for (ddr_size = msize << 20, ddr_size_log2 = 0;
+ (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++)
+ if (ddr_size & 1)
+ return -1;
+ im->sysconf.ddrlaw[0].ar =
+ LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
+ im->ddr.csbnds[0].csbnds = (((msize / 16) - 1) & 0xff);
+ }
+
return msize;
}
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index a23c9ed..ef3faa5 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -92,8 +92,8 @@
* Manually set up DDR parameters
*/
#define CONFIG_DDR_II
-#define CONFIG_SYS_DDR_SIZE 256 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
+#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)