dm: x86: quark: Add an interrupt driver
Add a driver for interrupts on quark and move the code currently in
cpu_irq_init() into its probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index 8f1d018..6d670d7 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += car.o dram.o msg_port.o quark.o
+obj-y += car.o dram.o irq.o msg_port.o quark.o
obj-y += mrc.o mrc_util.o hte.o smc.o
diff --git a/arch/x86/cpu/quark/irq.c b/arch/x86/cpu/quark/irq.c
new file mode 100644
index 0000000..1f8f909
--- /dev/null
+++ b/arch/x86/cpu/quark/irq.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/irq.h>
+#include <asm/arch/device.h>
+#include <asm/arch/quark.h>
+
+int quark_irq_router_probe(struct udevice *dev)
+{
+ struct quark_rcba *rcba;
+ u32 base;
+
+ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct quark_rcba *)base;
+
+ /*
+ * Route Quark PCI device interrupt pin to PIRQ
+ *
+ * Route device#23's INTA/B/C/D to PIRQA/B/C/D
+ * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
+ */
+ writew(PIRQC, &rcba->rmu_ir);
+ writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
+ &rcba->d23_ir);
+ writew(PIRQD, &rcba->core_ir);
+ writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
+ &rcba->d20d21_ir);
+
+ return irq_router_common_init(dev);
+}
+
+static const struct udevice_id quark_irq_router_ids[] = {
+ { .compatible = "intel,quark-irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(quark_irq_router_drv) = {
+ .name = "quark_intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = quark_irq_router_ids,
+ .probe = quark_irq_router_probe,
+};
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 28370d1..6e20930 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -7,12 +7,10 @@
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
-#include <asm/irq.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/post.h>
-#include <asm/processor.h>
#include <asm/arch/device.h>
#include <asm/arch/msg_port.h>
#include <asm/arch/quark.h>
@@ -346,29 +344,6 @@
return pci_mmc_init("Quark SDHCI", mmc_supported);
}
-void cpu_irq_init(void)
-{
- struct quark_rcba *rcba;
- u32 base;
-
- qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
- base &= ~MEM_BAR_EN;
- rcba = (struct quark_rcba *)base;
-
- /*
- * Route Quark PCI device interrupt pin to PIRQ
- *
- * Route device#23's INTA/B/C/D to PIRQA/B/C/D
- * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
- */
- writew(PIRQC, &rcba->rmu_ir);
- writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
- &rcba->d23_ir);
- writew(PIRQD, &rcba->core_ir);
- writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
- &rcba->d20d21_ir);
-}
-
int arch_misc_init(void)
{
#ifdef CONFIG_ENABLE_MRC_CACHE
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 9d82bb3..a2f5a1f 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -84,7 +84,7 @@
compatible = "intel,pch7";
irq-router {
- compatible = "intel,irq-router";
+ compatible = "intel,quark-irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
intel,pirq-mask = <0xdef8>;