| commit | 116f75c7b310bb5087195416e309d5a292e04560 | [log] [tgz] |
|---|---|---|
| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | Wed Sep 04 06:25:44 2019 +0000 |
| committer | Priyanka Jain <priyanka.jain@nxp.com> | Thu Sep 12 16:15:42 2019 +0530 |
| tree | 53fd86aa38d28853e8c351cc2d96ed4be5bba36a | |
| parent | c9ba88bafc786a258f64ce673fc63b9e5994c88a [diff] |
armv8: ls1028a: Updated serdes configuration for 0x13BB
In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2
Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes
protocal support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>