powerpc 86xx: Handle CCSR relocation earlier
Currently, the CCSR gets relocated while translation is
enabled, meaning we need 2 BAT translations to get to both the
old location and the new location. Also, the DEFAULT
CCSR location has a dependency on the BAT that maps the
FLASH region. Moving the relocation removes this unnecessary
dependency. This makes it easier and more intutive to
modify the board's memory map.
Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same
BAT for CCSR space.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 67b2764..6f04127 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -370,27 +370,29 @@
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
/*
- * BAT3 32M Cache-inhibited, guarded
+ * BAT3 4M Cache-inhibited, guarded
+ * 0xe000_0000 4M CCSR
+ */
+
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
+ | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
+
+/*
+ * BAT4 32M Cache-inhibited, guarded
* 0xe200_0000 1M PCI-Express 2 I/O
* 0xe300_0000 1M PCI-Express 1 I/O
*/
-#define CONFIG_SYS_DBAT3L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT3U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
-
-/*
- * BAT4 4M Cache-inhibited, guarded
- * 0xe000_0000 4M CCSR
- */
-#define CONFIG_SYS_DBAT4L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
+
/*
* BAT5 128K Cacheable, non-guarded
* 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)