diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index c8b72eb..6de31e8 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -22,12 +22,26 @@
 	help
 	  Do not enable instruction cache in U-Boot.
 
+config SPL_SYS_ICACHE_OFF
+	bool "Do not enable icache in SPL"
+	depends on SPL
+	default SYS_ICACHE_OFF
+	help
+	  Do not enable instruction cache in SPL.
+
 config SYS_DCACHE_OFF
 	bool "Do not enable dcache"
 	default n
 	help
 	  Do not enable data cache in U-Boot.
 
+config SPL_SYS_DCACHE_OFF
+	bool "Do not enable dcache in SPL"
+	depends on SPL
+	default SYS_DCACHE_OFF
+	help
+	  Do not enable data cache in SPL.
+
 source "board/cadence/xtfpga/Kconfig"
 
 endmenu
diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S
index 0fafb1c..38d2fa2 100644
--- a/arch/xtensa/cpu/start.S
+++ b/arch/xtensa/cpu/start.S
@@ -164,18 +164,19 @@
 	 * enable data/instruction cache for relocated image.
 	 */
 #if XCHAL_HAVE_SPANNING_WAY && \
-	!(defined(CONFIG_SYS_DCACHE_OFF) && defined(CONFIG_SYS_ICACHE_OFF))
+	!(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \
+	  CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
 	srli	a7, a4, 29
 	slli	a7, a7, 29
 	addi	a7, a7, XCHAL_SPANNING_WAY
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 	rdtlb1	a8, a7
 	srli	a8, a8, 4
 	slli	a8, a8, 4
 	addi	a8, a8, CA_WRITEBACK
 	wdtlb	a8, a7
 #endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 	ritlb1	a8, a7
 	srli	a8, a8, 4
 	slli	a8, a8, 4