CONFIG_SPL_SYS_[DI]CACHE_OFF: add
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6f510cc..00be3d1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -80,12 +80,26 @@
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
config SYS_ARM_CACHE_CP15
bool "CP15 based cache enabling support"
help
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 4aa704b..8aee153 100644
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -51,7 +51,7 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
@@ -87,7 +87,7 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -95,15 +95,15 @@
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 22a55f5..16eea69 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@@ -46,7 +46,7 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -54,7 +54,7 @@
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
@@ -66,7 +66,7 @@
__weak void invalidate_l2_cache(void) {}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
@@ -80,10 +80,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index c3f1ee1..d7cffe8 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -44,7 +44,7 @@
/* flush I/D-cache */
static void cache_flush (void)
{
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 1045673..ff592ba 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -84,7 +84,7 @@
/*
* disable MMU and D cache
- * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
+ * enable I cache if SYS_ICACHE_OFF is not defined
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
@@ -95,7 +95,7 @@
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 99484c2..0dc4ebf 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -12,7 +12,7 @@
#define ARMV7_DCACHE_INVAL_RANGE 1
#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Asm functions from cache_v7_asm.S */
void v7_flush_dcache_all(void);
@@ -149,7 +149,7 @@
flush_dcache_range(start, stop);
v7_inval_tlb();
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -177,9 +177,9 @@
void arm_init_domains(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
index 8bf06a3..70431ec 100644
--- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
@@ -5,7 +5,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
index 8783893..10e7488 100644
--- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <linux/sizes.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 7c4018e..ecf9e86 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* Bit[1] of the descriptor indicates the descriptor type,
@@ -215,7 +215,7 @@
invalidate_dcache_all();
set_cr(get_cr() | CR_C);
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
uint get_svr(void)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 0cb6dd3..dcb4195 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -97,7 +97,7 @@
/*
* If I-cache is enabled invalidate it
*/
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
@@ -155,7 +155,7 @@
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
#else
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 90fa695..f962903 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -360,7 +360,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index 815e623..1106bea 100644
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -54,7 +54,7 @@
FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
};
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct dcache_config {
u32 ways;
u32 sets;
@@ -292,7 +292,7 @@
}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
@@ -349,10 +349,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 9ca397e..e500e72 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -13,7 +13,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* With 4k page granule, a virtual address is split into 4 lookup parts
@@ -657,7 +657,7 @@
__asm_invalidate_tlb_all();
}
-#else /* CONFIG_SYS_DCACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* For SPL builds, we may want to not have dcache enabled. Any real U-Boot
@@ -694,9 +694,9 @@
{
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable(void)
{
@@ -720,7 +720,7 @@
__asm_invalidate_l3_icache();
}
-#else /* CONFIG_SYS_ICACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
void icache_enable(void)
{
@@ -739,7 +739,7 @@
{
}
-#endif /* CONFIG_SYS_ICACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
/*
* Enable dCache & iCache, whether cache is actually enabled
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b..12d709e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -388,7 +388,7 @@
strcpy(name, "unknown");
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@ -611,7 +611,7 @@
icache_enable();
dcache_enable();
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)
diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
index 1fa6841..b4cb67a 100644
--- a/arch/arm/cpu/armv8/s32v234/cpu.c
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -16,7 +16,7 @@
return readl(MC_ME_CS);
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define S32V234_IRAM_BASE 0x3e800000UL
#define S32V234_IRAM_SIZE 0x800000UL
diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c
index 8b932b1..5cd4a95 100644
--- a/arch/arm/cpu/pxa/cache.c
+++ b/arch/arm/cpu/pxa/cache.c
@@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
@@ -35,7 +35,7 @@
{
return invalidate_dcache_range(start, stop);
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -43,7 +43,7 @@
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index b9fd41e..0b28f0a 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -286,10 +286,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index c3ee5f0..a81b106 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -35,7 +35,7 @@
unsigned int tbl;
unsigned long lastinc;
unsigned long long timer_reset_value;
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long tlb_addr;
unsigned long tlb_size;
#if defined(CONFIG_ARM64)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 0688f1e..b2913e8 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -10,7 +10,7 @@
#include <linux/compiler.h>
#include <asm/armv7_mpu.h>
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
DECLARE_GLOBAL_DATA_PTR;
@@ -246,7 +246,7 @@
}
#endif
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable (void)
{
return;
@@ -278,7 +278,7 @@
}
#endif
-#ifdef CONFIG_SYS_DCACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_enable (void)
{
return;
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 565fbbe..449544d 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -87,7 +87,7 @@
noncached_end = end;
noncached_next = start;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
#endif
}
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 589e16c..2ae9a43 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -25,7 +25,7 @@
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 75e1f54..a605942 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -37,7 +37,7 @@
}
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 2c42535..53f9a87 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -446,7 +446,7 @@
dcache_enable();
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c
index 43d6c08..bbb335e 100644
--- a/arch/arm/mach-imx/mx5/soc.c
+++ b/arch/arm/mach-imx/mx5/soc.c
@@ -62,7 +62,7 @@
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index f43b3dc..3dee300 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -204,7 +204,7 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 0777a0c..bb01eab 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -34,7 +34,7 @@
endif
endif
-ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif
diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
index 6dc92a6..32de9d3 100644
--- a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
+++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
@@ -16,7 +16,7 @@
.arch_extension sec
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.global flush_dcache_range
#endif
@@ -79,7 +79,7 @@
push {r4, r5, lr}
ldr r4, =omap_smc_sec_cpu1_args
stm r4, {r0,r1,r2,r3} @ Save args to memory
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mov r0, r4
mov r1, #CONFIG_SYS_CACHELINE_SIZE
add r1, r0, r1 @ dcache is not enabled on CPU1, so
@@ -109,7 +109,7 @@
*/
.section .data
omap_smc_sec_cpu1_args:
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.balign CONFIG_SYS_CACHELINE_SIZE
.rept CONFIG_SYS_CACHELINE_SIZE/4
.word 0
diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c
index 600a312..b45d3ee 100644
--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c
@@ -333,7 +333,7 @@
debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
debug("tee_file_size = %d\n", tee_file_size);
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range(
rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
@@ -356,7 +356,7 @@
/* Reuse the tee_info buffer for SMC params */
smc_cpu1_params = (u32 *)&tee_info;
smc_cpu1_params[0] = 0;
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
roundup(sizeof(u32), ARCH_DMA_MINALIGN));
#endif
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index b0686ed..784a2a2 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -17,7 +17,7 @@
/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_GEN3
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c
index 2094a43..e6ea0e9 100644
--- a/arch/arm/mach-rockchip/rk3036-board.c
+++ b/arch/arm/mach-rockchip/rk3036-board.c
@@ -48,7 +48,7 @@
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
index b1c6638..fa71685 100644
--- a/arch/arm/mach-rockchip/rk3128-board.c
+++ b/arch/arm/mach-rockchip/rk3128-board.c
@@ -57,7 +57,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
index e03759f..80d8c42 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -75,7 +75,7 @@
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
index 6170c76..e7a1e54 100644
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ b/arch/arm/mach-rockchip/rk322x-board.c
@@ -58,7 +58,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 41e9786..e2de5b2 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -186,7 +186,7 @@
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c
index 33596f6..66aeb3f 100644
--- a/arch/arm/mach-rockchip/rv1108/rv1108.c
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -6,7 +6,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c
index 12c9d7c..0b879b5 100644
--- a/arch/arm/mach-s5pc1xx/cache.c
+++ b/arch/arm/mach-s5pc1xx/cache.c
@@ -9,7 +9,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index d887f02..db1983d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -48,10 +48,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index c6dd7b8..7f5b633 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -300,7 +300,7 @@
#endif
}
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index f8fc042..4e15907 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -226,7 +226,7 @@
};
#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index a3422cd..e5f55771 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -83,7 +83,7 @@
;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */