CONFIG_SPL_SYS_[DI]CACHE_OFF: add
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 240d3bb..0cb9720 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -114,12 +114,26 @@
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
menuconfig ARC_DBG
bool "ARC debugging"
default n
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 84959b4..8c744f5 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -16,7 +16,7 @@
lr r5, [ARC_BCR_IC_BUILD]
breq r5, 0, 1f ; I$ doesn't exist
lr r5, [ARC_AUX_IC_CTRL]
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
#else
bset r5, r5, 0 ; I$ exists, but is not used
@@ -37,7 +37,7 @@
breq r5, 0, 1f ; D$ doesn't exist
lr r5, [ARC_AUX_DC_CTRL]
bclr r5, r5, 6 ; Invalidate (discard w/o wback)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
bclr r5, r5, 0 ; Enable (+Inv)
#else
bset r5, r5, 0 ; Disable (+Inv)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6f510cc..00be3d1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -80,12 +80,26 @@
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
config SYS_ARM_CACHE_CP15
bool "CP15 based cache enabling support"
help
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
index 4aa704b..8aee153 100644
--- a/arch/arm/cpu/arm11/cpu.c
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -51,7 +51,7 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
@@ -87,7 +87,7 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -95,15 +95,15 @@
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 22a55f5..16eea69 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
@@ -46,7 +46,7 @@
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -54,7 +54,7 @@
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
@@ -66,7 +66,7 @@
__weak void invalidate_l2_cache(void) {}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
@@ -80,10 +80,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index c3f1ee1..d7cffe8 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arch/arm/cpu/arm926ejs/cpu.c
@@ -44,7 +44,7 @@
/* flush I/D-cache */
static void cache_flush (void)
{
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 1045673..ff592ba 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -84,7 +84,7 @@
/*
* disable MMU and D cache
- * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
+ * enable I cache if SYS_ICACHE_OFF is not defined
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
@@ -95,7 +95,7 @@
bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
#endif
orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
#endif
mcr p15, 0, r0, c1, c0, 0
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 99484c2..0dc4ebf 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -12,7 +12,7 @@
#define ARMV7_DCACHE_INVAL_RANGE 1
#define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Asm functions from cache_v7_asm.S */
void v7_flush_dcache_all(void);
@@ -149,7 +149,7 @@
flush_dcache_range(start, stop);
v7_inval_tlb();
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -177,9 +177,9 @@
void arm_init_domains(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
/* Invalidate entire I-cache and branch predictor array */
void invalidate_icache_all(void)
{
diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
index 8bf06a3..70431ec 100644
--- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c
@@ -5,7 +5,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
index 8783893..10e7488 100644
--- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <linux/sizes.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 7c4018e..ecf9e86 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -26,7 +26,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* Bit[1] of the descriptor indicates the descriptor type,
@@ -215,7 +215,7 @@
invalidate_dcache_all();
set_cr(get_cr() | CR_C);
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
uint get_svr(void)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 0cb6dd3..dcb4195 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -97,7 +97,7 @@
/*
* If I-cache is enabled invalidate it
*/
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
mcr p15, 0, r0, c7, c10, 4 @ DSB
mcr p15, 0, r0, c7, c5, 4 @ ISB
@@ -155,7 +155,7 @@
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
#else
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 90fa695..f962903 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -360,7 +360,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index 815e623..1106bea 100644
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -54,7 +54,7 @@
FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
};
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct dcache_config {
u32 ways;
u32 sets;
@@ -292,7 +292,7 @@
}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
@@ -349,10 +349,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 9ca397e..e500e72 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -13,7 +13,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* With 4k page granule, a virtual address is split into 4 lookup parts
@@ -657,7 +657,7 @@
__asm_invalidate_tlb_all();
}
-#else /* CONFIG_SYS_DCACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* For SPL builds, we may want to not have dcache enabled. Any real U-Boot
@@ -694,9 +694,9 @@
{
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable(void)
{
@@ -720,7 +720,7 @@
__asm_invalidate_l3_icache();
}
-#else /* CONFIG_SYS_ICACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
void icache_enable(void)
{
@@ -739,7 +739,7 @@
{
}
-#endif /* CONFIG_SYS_ICACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
/*
* Enable dCache & iCache, whether cache is actually enabled
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b..12d709e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -388,7 +388,7 @@
strcpy(name, "unknown");
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@ -611,7 +611,7 @@
icache_enable();
dcache_enable();
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
#ifdef CONFIG_TFABOOT
enum boot_src __get_boot_src(u32 porsr1)
diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
index 1fa6841..b4cb67a 100644
--- a/arch/arm/cpu/armv8/s32v234/cpu.c
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -16,7 +16,7 @@
return readl(MC_ME_CS);
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define S32V234_IRAM_BASE 0x3e800000UL
#define S32V234_IRAM_SIZE 0x800000UL
diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c
index 8b932b1..5cd4a95 100644
--- a/arch/arm/cpu/pxa/cache.c
+++ b/arch/arm/cpu/pxa/cache.c
@@ -6,7 +6,7 @@
#include <linux/types.h>
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
@@ -35,7 +35,7 @@
{
return invalidate_dcache_range(start, stop);
}
-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
void invalidate_dcache_all(void)
{
}
@@ -43,7 +43,7 @@
void flush_dcache_all(void)
{
}
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* Stub implementations for l2 cache operations
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index b9fd41e..0b28f0a 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -286,10 +286,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index c3ee5f0..a81b106 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -35,7 +35,7 @@
unsigned int tbl;
unsigned long lastinc;
unsigned long long timer_reset_value;
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
unsigned long tlb_addr;
unsigned long tlb_size;
#if defined(CONFIG_ARM64)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 0688f1e..b2913e8 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -10,7 +10,7 @@
#include <linux/compiler.h>
#include <asm/armv7_mpu.h>
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
DECLARE_GLOBAL_DATA_PTR;
@@ -246,7 +246,7 @@
}
#endif
-#ifdef CONFIG_SYS_ICACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable (void)
{
return;
@@ -278,7 +278,7 @@
}
#endif
-#ifdef CONFIG_SYS_DCACHE_OFF
+#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_enable (void)
{
return;
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 565fbbe..449544d 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -87,7 +87,7 @@
noncached_end = end;
noncached_next = start;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
#endif
}
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 589e16c..2ae9a43 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -25,7 +25,7 @@
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 75e1f54..a605942 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -37,7 +37,7 @@
}
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 2c42535..53f9a87 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -446,7 +446,7 @@
dcache_enable();
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
u64 get_page_table_size(void)
{
u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c
index 43d6c08..bbb335e 100644
--- a/arch/arm/mach-imx/mx5/soc.c
+++ b/arch/arm/mach-imx/mx5/soc.c
@@ -62,7 +62,7 @@
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index f43b3dc..3dee300 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -204,7 +204,7 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 0777a0c..bb01eab 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -34,7 +34,7 @@
endif
endif
-ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
obj-y += omap-cache.o
endif
diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
index 6dc92a6..32de9d3 100644
--- a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
+++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
@@ -16,7 +16,7 @@
.arch_extension sec
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.global flush_dcache_range
#endif
@@ -79,7 +79,7 @@
push {r4, r5, lr}
ldr r4, =omap_smc_sec_cpu1_args
stm r4, {r0,r1,r2,r3} @ Save args to memory
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
mov r0, r4
mov r1, #CONFIG_SYS_CACHELINE_SIZE
add r1, r0, r1 @ dcache is not enabled on CPU1, so
@@ -109,7 +109,7 @@
*/
.section .data
omap_smc_sec_cpu1_args:
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
.balign CONFIG_SYS_CACHELINE_SIZE
.rept CONFIG_SYS_CACHELINE_SIZE/4
.word 0
diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c
index 600a312..b45d3ee 100644
--- a/arch/arm/mach-omap2/sec-common.c
+++ b/arch/arm/mach-omap2/sec-common.c
@@ -333,7 +333,7 @@
debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
debug("tee_file_size = %d\n", tee_file_size);
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range(
rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
@@ -356,7 +356,7 @@
/* Reuse the tee_info buffer for SMC params */
smc_cpu1_params = (u32 *)&tee_info;
smc_cpu1_params[0] = 0;
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
roundup(sizeof(u32), ARCH_DMA_MINALIGN));
#endif
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index b0686ed..784a2a2 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -17,7 +17,7 @@
/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
#ifndef CONFIG_RCAR_GEN3
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c
index 2094a43..e6ea0e9 100644
--- a/arch/arm/mach-rockchip/rk3036-board.c
+++ b/arch/arm/mach-rockchip/rk3036-board.c
@@ -48,7 +48,7 @@
}
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c
index b1c6638..fa71685 100644
--- a/arch/arm/mach-rockchip/rk3128-board.c
+++ b/arch/arm/mach-rockchip/rk3128-board.c
@@ -57,7 +57,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
index e03759f..80d8c42 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -75,7 +75,7 @@
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
index 6170c76..e7a1e54 100644
--- a/arch/arm/mach-rockchip/rk322x-board.c
+++ b/arch/arm/mach-rockchip/rk322x-board.c
@@ -58,7 +58,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 41e9786..e2de5b2 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -186,7 +186,7 @@
#endif
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c
index 33596f6..66aeb3f 100644
--- a/arch/arm/mach-rockchip/rv1108/rv1108.c
+++ b/arch/arm/mach-rockchip/rv1108/rv1108.c
@@ -6,7 +6,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c
index 12c9d7c..0b879b5 100644
--- a/arch/arm/mach-s5pc1xx/cache.c
+++ b/arch/arm/mach-s5pc1xx/cache.c
@@ -9,7 +9,7 @@
#include <common.h>
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
dcache_enable();
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index d887f02..db1983d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -48,10 +48,10 @@
void enable_caches(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
dcache_enable();
#endif
}
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index c6dd7b8..7f5b633 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -300,7 +300,7 @@
#endif
}
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index f8fc042..4e15907 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -226,7 +226,7 @@
};
#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index a3422cd..e5f55771 100644
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -83,7 +83,7 @@
;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
index 89d8af5..b6f16bf 100644
--- a/arch/nds32/Kconfig
+++ b/arch/nds32/Kconfig
@@ -22,12 +22,26 @@
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
source "board/AndesTech/adp-ag101p/Kconfig"
source "board/AndesTech/adp-ae3xx/Kconfig"
diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S
index 4e6a0e7..6918881 100644
--- a/arch/nds32/cpu/n1213/start.S
+++ b/arch/nds32/cpu/n1213/start.S
@@ -129,7 +129,7 @@
mfsr $r1, $mr8
and $r1, $r1, $r0
mtsr $r1, $mr8
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/*
* MMU_CTL NTC0 Cacheable/Write-Back
*/
@@ -139,7 +139,7 @@
mtsr $r1, $mr0
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_ARCH_MAP_SYSMEM
/*
* MMU_CTL NTC1 Non-cacheable
@@ -158,14 +158,14 @@
#endif
#endif
-#if !defined(CONFIG_SYS_ICACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
li $r0, 0x1
mfsr $r1, $mr8
or $r1, $r1, $r0
mtsr $r1, $mr8
#endif
-#if !defined(CONFIG_SYS_DCACHE_OFF)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
li $r0, 0x2
mfsr $r1, $mr8
or $r1, $r1, $r0
diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c
index 3e5aa7c..2706513 100644
--- a/arch/nds32/lib/cache.c
+++ b/arch/nds32/lib/cache.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
static inline unsigned long CACHE_SET(unsigned char cache)
{
if (cache == ICACHE)
@@ -38,7 +38,7 @@
}
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void invalidate_icache_all(void)
{
unsigned long end, line_size;
@@ -133,7 +133,7 @@
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void dcache_wbinval_all(void)
{
unsigned long end, line_size;
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c993809..0d04d91 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -25,12 +25,26 @@
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 228fc55..cd95058 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -30,7 +30,7 @@
void icache_enable(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
@@ -43,7 +43,7 @@
void icache_disable(void)
{
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence.i\n\t"
@@ -57,7 +57,7 @@
void dcache_enable(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"csrr t1, mcache_ctl\n\t"
@@ -70,7 +70,7 @@
void dcache_disable(void)
{
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#ifdef CONFIG_RISCV_NDS_CACHE
asm volatile (
"fence\n\t"
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index c8b72eb..6de31e8 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -22,12 +22,26 @@
help
Do not enable instruction cache in U-Boot.
+config SPL_SYS_ICACHE_OFF
+ bool "Do not enable icache in SPL"
+ depends on SPL
+ default SYS_ICACHE_OFF
+ help
+ Do not enable instruction cache in SPL.
+
config SYS_DCACHE_OFF
bool "Do not enable dcache"
default n
help
Do not enable data cache in U-Boot.
+config SPL_SYS_DCACHE_OFF
+ bool "Do not enable dcache in SPL"
+ depends on SPL
+ default SYS_DCACHE_OFF
+ help
+ Do not enable data cache in SPL.
+
source "board/cadence/xtfpga/Kconfig"
endmenu
diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S
index 0fafb1c..38d2fa2 100644
--- a/arch/xtensa/cpu/start.S
+++ b/arch/xtensa/cpu/start.S
@@ -164,18 +164,19 @@
* enable data/instruction cache for relocated image.
*/
#if XCHAL_HAVE_SPANNING_WAY && \
- !(defined(CONFIG_SYS_DCACHE_OFF) && defined(CONFIG_SYS_ICACHE_OFF))
+ !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \
+ CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
srli a7, a4, 29
slli a7, a7, 29
addi a7, a7, XCHAL_SPANNING_WAY
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
rdtlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4
addi a8, a8, CA_WRITEBACK
wdtlb a8, a7
#endif
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
ritlb1 a8, a7
srli a8, a8, 4
slli a8, a8, 4
diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c
index b4fc8f3..111e64b 100644
--- a/board/st/stih410-b2260/board.c
+++ b/board/st/stih410-b2260/board.c
@@ -26,7 +26,7 @@
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index cbeba6b..f576e22 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -321,7 +321,7 @@
print_eths();
#endif
print_baudrate();
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
print_num("TLB addr", gd->arch.tlb_addr);
#endif
print_num("relocaddr", gd->relocaddr);
diff --git a/common/board_f.c b/common/board_f.c
index 7ef20f2..c25eb18 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -381,7 +381,7 @@
#ifdef CONFIG_ARM
__weak int reserve_mmu(void)
{
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
+#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
gd->relocaddr -= gd->arch.tlb_size;
diff --git a/common/lcd.c b/common/lcd.c
index cd63040..95526b1 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -61,7 +61,7 @@
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
int line_length;
if (lcd_flush_dcache)
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index bcc5a0a..73febdf 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig
index 63acd28..3787a95 100644
--- a/configs/bitmain_antminer_s9_defconfig
+++ b/configs/bitmain_antminer_s9_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_BOARD="antminer_s9"
CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_ENV_OFFSET=0x300000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 6811a62..7383124 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_IMX8MQ_EVK=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 238d44d..1a6ce3a 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 59675e5..c4a8cf3 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -1,5 +1,7 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 005b6e9..ffe50b1 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -2,6 +2,8 @@
CONFIG_SPL_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23000000
CONFIG_TARGET_SMARTWEB=y
diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig
index 896232a..5616b3e 100644
--- a/configs/syzygy_hub_defconfig
+++ b/configs/syzygy_hub_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_VENDOR="opalkelly"
CONFIG_SYS_CONFIG_NAME="syzygy_hub"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 02a8959..8af7dd7 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -2,6 +2,8 @@
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_AT91=y
CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x21000000
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index b558856..bb8d37a 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index 6983245..87af8c8 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 89461ee..874ca8a 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -2,6 +2,7 @@
CONFIG_SYS_VENDOR="topic"
CONFIG_SYS_CONFIG_NAME="topic_miami"
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
CONFIG_SPL=y
diff --git a/configs/zynq_cc108_defconfig b/configs/zynq_cc108_defconfig
index 089df8d..966bb150 100644
--- a/configs/zynq_cc108_defconfig
+++ b/configs/zynq_cc108_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig
index 62ed8f73..76b85d4 100644
--- a/configs/zynq_cse_nand_defconfig
+++ b/configs/zynq_cse_nand_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig
index 2e9a54e..fad7b5d 100644
--- a/configs/zynq_cse_nor_defconfig
+++ b/configs/zynq_cse_nor_defconfig
@@ -3,6 +3,7 @@
CONFIG_SYS_ICACHE_OFF=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_dlc20_rev1_0_defconfig b/configs/zynq_dlc20_rev1_0_defconfig
index 913581e..f9d2b31 100644
--- a/configs/zynq_dlc20_rev1_0_defconfig
+++ b/configs/zynq_dlc20_rev1_0_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 83fa967..5e7ff16 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig
index 809fa91..f253483 100644
--- a/configs/zynq_minized_defconfig
+++ b/configs/zynq_minized_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index 09d78dc..0650ce2 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_z_turn_defconfig b/configs/zynq_z_turn_defconfig
index f24fe31..4839ee2 100644
--- a/configs/zynq_z_turn_defconfig
+++ b/configs/zynq_z_turn_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 748b080..71559b0 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 9b0ddb0..132ef6c 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 8653d7a..8ba35cb 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index eb25836..84f46a7 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm011_x16_defconfig b/configs/zynq_zc770_xm011_x16_defconfig
index 4e40339..43ff1f4 100644
--- a/configs/zynq_zc770_xm011_x16_defconfig
+++ b/configs/zynq_zc770_xm011_x16_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 868b73b..2adf686 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index b1d19f1..ed6506d 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 09fc1c3..2da6d40b 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index 607bc27..b51272b 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/configs/zynq_zybo_z7_defconfig b/configs/zynq_zybo_z7_defconfig
index 81da0d2..4deb14e 100644
--- a/configs/zynq_zybo_z7_defconfig
+++ b/configs/zynq_zybo_z7_defconfig
@@ -1,4 +1,5 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SPL_STACK_R_ADDR=0x200000
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 017cc89..ac589fe 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -81,7 +81,7 @@
return tmp;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
{
uint32_t addr;
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index be4ee2c..b93d77a 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -50,7 +50,7 @@
/*
* Cache management functions
*/
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
{
uint32_t addr = (uint32_t)info->data_buf;
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9f1c5af..590e756 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -241,7 +241,7 @@
*/
#if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
- !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning Cache line size is larger than descriptor size
#endif
#endif
diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index bc052e7..521e590 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -302,7 +302,7 @@
*/
#if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
#if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
- !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
#warning cache-line size is larger than descriptor size
#endif
#endif
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 8e54e7c..da79b76 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -34,7 +34,8 @@
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
-#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
+ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define flush_cache_wback(addr, len) \
flush_dcache_range((u32)addr, \
(u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c
index 14aac88..b19bfb4 100644
--- a/drivers/video/video-uclass.c
+++ b/drivers/video/video-uclass.c
@@ -149,7 +149,7 @@
* architectures do not actually implement it. Is there a way to find
* out whether it exists? For now, ARM is safe.
*/
-#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
struct video_priv *priv = dev_get_uclass_priv(vid);
if (priv->flush_dcache) {
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 5bd6392..2af5a4f 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -167,7 +167,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
#define CONFIG_CMD_CACHE
#endif
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 0d0c6bd..776d7d7 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -216,11 +216,6 @@
#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
#define CONFIG_SYS_AT91_PLLB 0x10483f0e
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 45a4a80..dbb01af 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -21,10 +21,6 @@
#include <asm/hardware.h>
#include <linux/sizes.h>
-#if defined(CONFIG_SPL_BUILD)
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
-#endif
/*
* Warning: changing CONFIG_SYS_TEXT_BASE requires
* adapting the initial boot program.
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 523d4da..143dc7b 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -284,11 +284,6 @@
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
-/* Disable dcache for SPL just for sure */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_DCACHE_OFF
-#endif
-
/* Address in RAM where the parameters must be copied by SPL. */
#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000