| commit | 0e4c1dd29026ee76b2ae8fb27a99366ac7d0b289 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Wed Jul 18 13:27:24 2018 +0200 |
| committer | Michal Simek <michal.simek@xilinx.com> | Tue Oct 16 14:58:45 2018 +0200 |
| tree | 5c79372be4b2ccad94cee1721ca8de0325a2c9fa | |
| parent | 3313ae668e0071f91cdf305fedb39b960beab62d [diff] |
arm: zynq: Enable FIT fpga loading in SPL for zc706 Enable loading FPGA from FIT image in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>