* Patch by Andrea Scian, 17 Feb 2004:
Add support for S3C44B0 processor and DAVE B2 board
* Patch by Steven Scholz, 20 Feb 2004:
- Add support for MII commands on AT91RM9200 boards
- some cleanup in AT91RM9200 ethernet code
diff --git a/cpu/at91rm9200/at91rm9200_ether.c b/cpu/at91rm9200/at91rm9200_ether.c
index 347a57b..3428a9e 100644
--- a/cpu/at91rm9200/at91rm9200_ether.c
+++ b/cpu/at91rm9200/at91rm9200_ether.c
@@ -310,8 +310,9 @@
unsigned short *pInput)
{
p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
- (AT91C_EMAC_CODE_802_3) | (AT91C_EMAC_RW_R) |
- (RegisterAddress << 18);
+ (AT91C_EMAC_RW_R) |
+ (RegisterAddress << 18) |
+ (AT91C_EMAC_CODE_802_3);
udelay (10000);
@@ -421,8 +422,14 @@
p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
- p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_RMII)
+
+ p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
& ~AT91C_EMAC_CLK;
+
+#ifdef CONFIG_AT91C_USE_RMII
+ p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
+#endif
+
p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
return 0;
@@ -462,5 +469,25 @@
void eth_halt (void)
{
};
+
+#if (CONFIG_COMMANDS & CFG_CMD_MII)
+int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
+{
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacReadPhy (p_mac, reg, value);
+ at91rm9200_EmacDisableMDIO (p_mac);
+ return 0;
+}
+
+int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
+{
+ at91rm9200_EmacEnableMDIO (p_mac);
+ at91rm9200_EmacWritePhy (p_mac, reg, &value);
+ at91rm9200_EmacDisableMDIO (p_mac);
+ return 0;
+}
+#endif /* CONFIG_COMMANDS & CFG_CMD_MII */
+
#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+
#endif /* CONFIG_DRIVER_ETHER */
diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile
new file mode 100644
index 0000000..d43c73e
--- /dev/null
+++ b/cpu/s3c44b0/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o
+OBJS = serial.o interrupts.o cpu.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/cpu/s3c44b0/config.mk b/cpu/s3c44b0/config.mk
new file mode 100644
index 0000000..a1c5dd1
--- /dev/null
+++ b/cpu/s3c44b0/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi -msoft-float
diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c
new file mode 100644
index 0000000..1a8a17d
--- /dev/null
+++ b/cpu/s3c44b0/cpu.c
@@ -0,0 +1,511 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * S3C44B0 CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/hardware.h>
+
+static void s3c44b0_flush_cache(void)
+{
+ volatile int i;
+ /* flush cycle */
+ for(i=0x10002000;i<0x10004800;i+=16)
+ {
+ *((int *)i)=0x0;
+ }
+}
+
+
+int cpu_init (void)
+{
+ icache_enable();
+
+ return 0;
+}
+
+int cleanup_before_linux (void)
+{
+ /*
+ cache memory should be enabled before calling
+ Linux to make the kernel uncompression faster
+ */
+ icache_enable();
+
+ disable_interrupts ();
+
+ return 0;
+}
+
+void reset_cpu (ulong addr)
+{
+ /*
+ reset the cpu using watchdog
+ */
+
+ /* Disable the watchdog.*/
+ WTCON&=~(1<<5);
+
+ /* set the timeout value to a short time... */
+ WTCNT = 0x1;
+
+ /* Enable the watchdog. */
+ WTCON|=1;
+ WTCON|=(1<<5);
+
+ while(1) {
+ /*NOP*/
+ }
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ extern void reset_cpu (ulong addr);
+
+ disable_interrupts ();
+ reset_cpu (0);
+
+ /*NOTREACHED*/
+ return (0);
+}
+
+void icache_enable (void)
+{
+ ulong reg;
+
+ s3c44b0_flush_cache();
+
+ /*
+ Init cache
+ Non-cacheable area (everything outside RAM)
+ 0x0000:0000 - 0x0C00:0000
+ */
+ NCACHBE0 = 0xC0000000;
+ NCACHBE1 = 0x00000000;
+
+ /*
+ Enable chache
+ */
+ reg = SYSCFG;
+ reg |= 0x00000006; /* 8kB */
+ SYSCFG = reg;
+}
+
+void icache_disable (void)
+{
+ ulong reg;
+
+ reg = SYSCFG;
+ reg &= ~0x00000006; /* 8kB */
+ SYSCFG = reg;
+}
+
+int icache_status (void)
+{
+ return 0;
+}
+
+void dcache_enable (void)
+{
+ icache_enable();
+}
+
+void dcache_disable (void)
+{
+ icache_disable();
+}
+
+int dcache_status (void)
+{
+ return dcache_status();
+}
+
+/*
+ RTC stuff
+*/
+#include <rtc.h>
+#ifndef BCD2HEX
+ #define BCD2HEX(n) ((n>>4)*10+(n&0x0f))
+#endif
+#ifndef HEX2BCD
+ #define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10)
+#endif
+
+void rtc_get (struct rtc_time* tm)
+{
+ RTCCON |= 1;
+ tm->tm_year = BCD2HEX(BCDYEAR);
+ tm->tm_mon = BCD2HEX(BCDMON);
+ tm->tm_wday = BCD2HEX(BCDDATE);
+ tm->tm_mday = BCD2HEX(BCDDAY);
+ tm->tm_hour = BCD2HEX(BCDHOUR);
+ tm->tm_min = BCD2HEX(BCDMIN);
+ tm->tm_sec = BCD2HEX(BCDSEC);
+
+ if (tm->tm_sec==0) {
+ /* we have to re-read the rtc data because of the "one second deviation" problem */
+ /* see RTC datasheet for more info about it */
+ tm->tm_year = BCD2HEX(BCDYEAR);
+ tm->tm_mon = BCD2HEX(BCDMON);
+ tm->tm_mday = BCD2HEX(BCDDAY);
+ tm->tm_wday = BCD2HEX(BCDDATE);
+ tm->tm_hour = BCD2HEX(BCDHOUR);
+ tm->tm_min = BCD2HEX(BCDMIN);
+ tm->tm_sec = BCD2HEX(BCDSEC);
+ }
+
+ RTCCON &= ~1;
+
+ if(tm->tm_year >= 70)
+ tm->tm_year += 1900;
+ else
+ tm->tm_year += 2000;
+}
+
+void rtc_set (struct rtc_time* tm)
+{
+ if(tm->tm_year < 2000)
+ tm->tm_year -= 1900;
+ else
+ tm->tm_year -= 2000;
+
+ RTCCON |= 1;
+ BCDYEAR = HEX2BCD(tm->tm_year);
+ BCDMON = HEX2BCD(tm->tm_mon);
+ BCDDAY = HEX2BCD(tm->tm_mday);
+ BCDDATE = HEX2BCD(tm->tm_wday);
+ BCDHOUR = HEX2BCD(tm->tm_hour);
+ BCDMIN = HEX2BCD(tm->tm_min);
+ BCDSEC = HEX2BCD(tm->tm_sec);
+ RTCCON &= 1;
+}
+
+void rtc_reset (void)
+{
+ RTCCON |= 1;
+ BCDYEAR = 0;
+ BCDMON = 0;
+ BCDDAY = 0;
+ BCDDATE = 0;
+ BCDHOUR = 0;
+ BCDMIN = 0;
+ BCDSEC = 0;
+ RTCCON &= 1;
+}
+
+
+/*
+ I2C stuff
+*/
+
+/*
+ * Initialization, must be called once on start up, may be called
+ * repeatedly to change the speed and slave addresses.
+ */
+void i2c_init(int speed, int slaveaddr)
+{
+ /*
+ setting up I2C support
+ */
+ unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF;
+
+ save_F = PCONF;
+ save_PF = PUPF;
+
+ rPCONF = ((save_F & ~(0xF))| 0xa);
+ rPUPF = (save_PF | 0x3);
+ PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/
+ PUPF = rPUPF; /* Disable pull-up */
+
+ /* Configuring pin for WC pin of EEprom */
+ rPCONA = PCONA;
+ rPCONA &= ~(1<<9);
+ PCONA = rPCONA;
+
+ rPDATA = PDATA;
+ rPDATA &= ~(1<<9);
+ PDATA = rPDATA;
+
+ /*
+ Enable ACK, IICCLK=MCLK/16, enable interrupt
+ 75Mhz/16/(12+1) = 390625 Hz
+ */
+ rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC);
+ IICCON = rIICCON;
+
+ IICADD = slaveaddr;
+}
+
+/*
+ * Probe the given I2C chip address. Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uchar chip)
+{
+ /*
+ not implemented
+ */
+
+ printf(__FUNCTION__ " chip %d\n", (int) chip);
+ return -1;
+}
+
+/*
+ * Read/Write interface:
+ * chip: I2C chip address, range 0..127
+ * addr: Memory (register) address within the chip
+ * alen: Number of bytes to use for addr (typically 1, 2 for larger
+ * memories, 0 for register type devices with only one
+ * register)
+ * buffer: Where to read/write the data
+ * len: How many bytes to read/write
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+
+#define S3C44B0X_rIIC_INTPEND (1<<4)
+#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0)
+#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5)
+#define S3C44B0_IIC_TIMEOUT 100
+
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+
+ int k, j, temp;
+ u32 rIICSTAT;
+
+ /*
+ send the device offset
+ */
+
+ rIICSTAT = 0xD0;
+ IICSTAT = rIICSTAT;
+
+ IICDS = chip; /* this is a write operation... */
+
+ rIICSTAT |= (1<<5);
+ IICSTAT = rIICSTAT;
+
+ for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
+ temp = IICCON;
+ if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
+ break;
+ udelay(2000);
+ }
+ if (k==S3C44B0_IIC_TIMEOUT)
+ return -1;
+
+ /* wait and check ACK */
+ temp = IICSTAT;
+ if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
+ return -1;
+
+ IICDS = addr;
+ IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
+
+ /* wait and check ACK */
+ for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
+ temp = IICCON;
+ if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
+ break;
+ udelay(2000);
+ }
+ if (k==S3C44B0_IIC_TIMEOUT)
+ return -1;
+
+ temp = IICSTAT;
+ if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
+ return -1;
+
+ /*
+ now we can start with the read operation...
+ */
+
+ IICDS = chip | 0x01; /* this is a read operation... */
+
+ rIICSTAT = 0x90; /*master recv*/
+ rIICSTAT |= (1<<5);
+ IICSTAT = rIICSTAT;
+
+ IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
+
+ /* wait and check ACK */
+ for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
+ temp = IICCON;
+ if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
+ break;
+ udelay(2000);
+ }
+ if (k==S3C44B0_IIC_TIMEOUT)
+ return -1;
+
+ temp = IICSTAT;
+ if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
+ return -1;
+
+ for (j=0; j<len-1; j++) {
+
+ /*clear pending bit to resume */
+
+ temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
+ IICCON = temp;
+
+ /* wait and check ACK */
+ for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
+ temp = IICCON;
+ if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
+ break;
+ udelay(2000);
+ }
+ if (k==S3C44B0_IIC_TIMEOUT)
+ return -1;
+
+
+ buffer[j] = IICDS; /*save readed data*/
+
+ } /*end for(j)*/
+
+ /*
+ reading the last data
+ unset ACK generation
+ */
+ temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7));
+ IICCON = temp;
+
+ /* wait but NOT check ACK */
+ for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
+ temp = IICCON;
+ if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
+ break;
+ udelay(2000);
+ }
+ if (k==S3C44B0_IIC_TIMEOUT)
+ return -1;
+
+ buffer[j] = IICDS; /*save readed data*/
+
+ rIICSTAT = 0x90; /*master recv*/
+
+ /* Write operation Terminate sending STOP */
+ IICSTAT = rIICSTAT;
+ /*Clear Int Pending Bit to RESUME*/
+ temp = IICCON;
+ IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
+
+ IICCON = IICCON | (1<<7); /*restore ACK generation*/
+
+ return 0;
+}
+
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ int j, k;
+ u32 rIICSTAT, temp;
+
+
+ /*
+ send the device offset
+ */
+
+ rIICSTAT = 0xD0;
+ IICSTAT = rIICSTAT;
+
+ IICDS = chip; /* this is a write operation... */
+
+ rIICSTAT |= (1<<5);
+ IICSTAT = rIICSTAT;
+
+ IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
+
+ /* wait and check ACK */
+ for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
+ temp = IICCON;
+ if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
+ break;
+ udelay(2000);
+ }
+ if (k==S3C44B0_IIC_TIMEOUT)
+ return -1;
+
+ temp = IICSTAT;
+ if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
+ return -1;
+
+ IICDS = addr;
+ IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
+
+ /* wait and check ACK */
+ for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
+ temp = IICCON;
+ if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
+ break;
+ udelay(2000);
+ }
+ if (k==S3C44B0_IIC_TIMEOUT)
+ return -1;
+
+ temp = IICSTAT;
+ if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
+ return -1;
+
+ /*
+ now we can start with the read write operation
+ */
+ for (j=0; j<len; j++) {
+
+ IICDS = buffer[j]; /*prerare data to write*/
+
+ /*clear pending bit to resume*/
+
+ temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
+ IICCON = temp;
+
+ /* wait but NOT check ACK */
+ for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
+ temp = IICCON;
+ if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
+ break;
+
+ udelay(2000);
+ }
+
+ if (k==S3C44B0_IIC_TIMEOUT)
+ return -1;
+
+ } /* end for(j) */
+
+ /* sending stop to terminate */
+ rIICSTAT = 0xD0; /*master send*/
+ IICSTAT = rIICSTAT;
+ /*Clear Int Pending Bit to RESUME*/
+ temp = IICCON;
+ IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
+
+ return 0;
+}
diff --git a/cpu/s3c44b0/interrupts.c b/cpu/s3c44b0/interrupts.c
new file mode 100644
index 0000000..4328feb
--- /dev/null
+++ b/cpu/s3c44b0/interrupts.c
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+#include <asm/proc-armv/ptrace.h>
+
+extern void reset_cpu(ulong addr);
+
+/* we always count down the max. */
+#define TIMER_LOAD_VAL 0xffff
+
+/* macro to read the 16 bit timer */
+#define READ_TIMER (TCNTO1 & 0xffff)
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ NOT supported
+#else
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+ panic ("Resetting CPU ...\n");
+ reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+ unsigned long flags;
+ const char *processor_modes[] =
+ { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
+ "UK6_26", "UK7_26",
+ "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
+ "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
+ "UK6_32", "ABT_32",
+ "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
+ "UK14_32", "SYS_32"
+ };
+
+ flags = condition_codes (regs);
+
+ printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
+ "sp : %08lx ip : %08lx fp : %08lx\n",
+ instruction_pointer (regs),
+ regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+ printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+ printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+ printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+ printf ("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+ printf (" IRQs %s FIQs %s Mode %s%s\n",
+ interrupts_enabled (regs) ? "on" : "off",
+ fast_interrupts_enabled (regs) ? "on" : "off",
+ processor_modes[processor_mode (regs)],
+ thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+ printf ("undefined instruction\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+ printf ("software interrupt\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+ printf ("prefetch abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+ printf ("data abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+ printf ("not used\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+ printf ("fast interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+ printf ("interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+int interrupt_init (void)
+{
+ TCFG0 = 0x000000E9;
+ TCFG1 = 0x00000004;
+ TCON = 0x00000900;
+ TCNTB1 = TIMER_LOAD_VAL;
+ TCMPB1 = 0;
+ TCON = 0x00000B00;
+ TCON = 0x00000900;
+
+
+ lastdec = TCNTB1 = TIMER_LOAD_VAL;
+ timestamp = 0;
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+void udelay (unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= CFG_HZ;
+ tmo /= 8;
+
+ tmo += get_timer (0);
+
+ while (get_timer_masked () < tmo)
+ /*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastdec = READ_TIMER;
+ timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+ ulong now = READ_TIMER;
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= CFG_HZ;
+ tmo /= 8;
+
+ tmo += get_timer (0);
+
+ reset_timer_masked ();
+
+ while (get_timer_masked () < tmo)
+ /*NOP*/;
+}
diff --git a/cpu/s3c44b0/serial.c b/cpu/s3c44b0/serial.c
new file mode 100644
index 0000000..61ccfc7
--- /dev/null
+++ b/cpu/s3c44b0/serial.c
@@ -0,0 +1,218 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+/* flush serial input queue. returns 0 on success or negative error
+ * number otherwise
+ */
+static int serial_flush_input(void)
+{
+ volatile u32 tmp;
+
+ /* keep on reading as long as the receiver is not empty */
+ while(UTRSTAT0&0x01) {
+ tmp = REGB(URXH0);
+ }
+
+ return 0;
+}
+
+
+/* flush output queue. returns 0 on success or negative error number
+ * otherwise
+ */
+static int serial_flush_output(void)
+{
+ /* wait until the transmitter is no longer busy */
+ while(!(UTRSTAT0 & 0x02)) {
+ }
+
+ return 0;
+}
+
+
+void serial_setbrg (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ u32 divisor = 0;
+
+ /* get correct divisor */
+ switch(gd->baudrate) {
+
+ case 1200:
+#if CONFIG_S3C44B0_CLOCK_SPEED==66
+ divisor = 3124;
+#elif CONFIG_S3C44B0_CLOCK_SPEED==75
+ divisor = 3905;
+#else
+# error CONFIG_S3C44B0_CLOCK_SPEED undefined
+#endif
+ break;
+
+ case 9600:
+#if CONFIG_S3C44B0_CLOCK_SPEED==66
+ divisor = 390;
+#elif CONFIG_S3C44B0_CLOCK_SPEED==75
+ divisor = 487;
+#else
+# error CONFIG_S3C44B0_CLOCK_SPEED undefined
+#endif
+ break;
+
+ case 19200:
+#if CONFIG_S3C44B0_CLOCK_SPEED==66
+ divisor = 194;
+#elif CONFIG_S3C44B0_CLOCK_SPEED==75
+ divisor = 243;
+#else
+# error CONFIG_S3C44B0_CLOCK_SPEED undefined
+#endif
+ break;
+
+ case 38400:
+#if CONFIG_S3C44B0_CLOCK_SPEED==66
+ divisor = 97;
+#elif CONFIG_S3C44B0_CLOCK_SPEED==75
+ divisor = 121;
+#else
+# error CONFIG_S3C44B0_CLOCK_SPEED undefined
+#endif break;
+
+ case 57600:
+#if CONFIG_S3C44B0_CLOCK_SPEED==66
+ divisor = 64;
+#elif CONFIG_S3C44B0_CLOCK_SPEED==75
+ divisor = 80;
+#else
+# error CONFIG_S3C44B0_CLOCK_SPEED undefined
+#endif break;
+
+ case 115200:
+#if CONFIG_S3C44B0_CLOCK_SPEED==66
+ divisor = 32;
+#elif CONFIG_S3C44B0_CLOCK_SPEED==75
+ divisor = 40;
+#else
+# error CONFIG_S3C44B0_CLOCK_SPEED undefined
+#endif break;
+ }
+
+ serial_flush_output();
+ serial_flush_input();
+ UFCON0 = 0x0;
+ ULCON0 = 0x03;
+ UCON0 = 0x05;
+ UBRDIV0 = divisor;
+
+ UFCON1 = 0x0;
+ ULCON1 = 0x03;
+ UCON1 = 0x05;
+ UBRDIV1 = divisor;
+
+ for(divisor=0; divisor<100; divisor++) {
+ /* NOP */
+ }
+}
+
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init (void)
+{
+ serial_setbrg ();
+
+ return (0);
+}
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc (const char c)
+{
+ /* wait for room in the transmit FIFO */
+ while(!(UTRSTAT0 & 0x02));
+
+ UTXH0 = (unsigned char)c;
+
+ /*
+ to be polite with serial console add a line feed
+ to the carriage return character
+ */
+ if (c=='\n')
+ serial_putc('\r');
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_tstc (void)
+{
+ return (UTRSTAT0 & 0x01);
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc (void)
+{
+ int rv;
+
+ for(;;) {
+ rv = serial_tstc();
+
+ if(rv > 0)
+ return URXH0;
+ }
+}
+
+void
+serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
diff --git a/cpu/s3c44b0/start.S b/cpu/s3c44b0/start.S
new file mode 100644
index 0000000..ce31ec9
--- /dev/null
+++ b/cpu/s3c44b0/start.S
@@ -0,0 +1,271 @@
+/*
+ * Startup Code for S3C44B0 CPU-core
+ *
+ * (C) Copyright 2004
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/*
+ * Jump vector table
+ */
+
+
+.globl _start
+_start: b reset
+ add pc, pc, #0x0c000000
+ add pc, pc, #0x0c000000
+ add pc, pc, #0x0c000000
+ add pc, pc, #0x0c000000
+ add pc, pc, #0x0c000000
+ add pc, pc, #0x0c000000
+ add pc, pc, #0x0c000000
+
+ .balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate u-boot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+ .word _start
+
+/*
+ * Note: _armboot_end_data and _armboot_end are defined
+ * by the (board-dependent) linker script.
+ * _armboot_end_data is the first usable FLASH address after armboot
+ */
+.globl _armboot_end_data
+_armboot_end_data:
+ .word armboot_end_data
+.globl _armboot_end
+_armboot_end:
+ .word armboot_end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0x13
+ msr cpsr,r0
+
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+
+#ifdef CONFIG_INIT_CRITICAL
+ bl cpu_init_crit
+ /*
+ * before relocating, we have to setup RAM timing
+ * because memory timing is board-dependend, you will
+ * find a memsetup.S in your board directory.
+ */
+ bl memsetup
+#endif
+
+relocate: /* relocate U-Boot to RAM */
+ adr r0, _start /* r0 <- current position of code */
+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
+
+ ldr r2, _armboot_start
+ ldr r3, _armboot_end
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+
+/*
+ now copy to sram the interrupt vector
+*/
+ adr r0, real_vectors
+ add r2, r0, #1024
+ ldr r1, =0x0c000000
+ add r1, r1, #0x08
+vector_copy_loop:
+ ldmia r0!, {r3-r10}
+ stmia r1!, {r3-r10}
+ cmp r0, r2
+ ble vector_copy_loop
+
+ /* Set up the stack */
+stack_setup:
+ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
+ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+#ifdef CONFIG_USE_IRQ
+ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
+ sub sp, r0, #12 /* leave 3 words for abort-stack */
+
+ ldr pc, _start_armboot
+
+_start_armboot: .word start_armboot
+
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+#define INTCON (0x01c00000+0x200000)
+#define INTMSK (0x01c00000+0x20000c)
+#define LOCKTIME (0x01c00000+0x18000c)
+#define PLLCON (0x01c00000+0x180000)
+#define CLKCON (0x01c00000+0x180004)
+#define WTCON (0x01c00000+0x130000)
+cpu_init_crit:
+ /* disable watch dog */
+ ldr r0, =WTCON
+ ldr r1, =0x0
+ str r1, [r0]
+
+ /*
+ * mask all IRQs by clearing all bits in the INTMRs
+ */
+ ldr r1,=INTMSK
+ ldr r0, =0x03fffeff
+ str r0, [r1]
+
+ ldr r1, =INTCON
+ ldr r0, =0x05
+ str r0, [r1]
+
+ /* Set Clock Control Register */
+ ldr r1, =LOCKTIME
+ ldrb r0, =800
+ strb r0, [r1]
+
+ ldr r1, =PLLCON
+
+#if CONFIG_S3C44B0_CLOCK_SPEED==66
+ ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
+#elif CONFIG_S3C44B0_CLOCK_SPEED==75
+ ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
+#else
+# error CONFIG_S3C44B0_CLOCK_SPEED undefined
+#endif
+
+ str r0, [r1]
+
+ ldr r1,=CLKCON
+ ldr r0, =0x7ff8
+ str r0, [r1]
+
+ mov pc, lr
+
+
+/*************************************************/
+/* interrupt vectors */
+/*************************************************/
+real_vectors:
+ b reset
+ b undefined_instruction
+ b software_interrupt
+ b prefetch_abort
+ b data_abort
+ b not_used
+ b irq
+ b fiq
+
+/*************************************************/
+
+undefined_instruction:
+ mov r6, #3
+ b reset
+
+software_interrupt:
+ mov r6, #4
+ b reset
+
+prefetch_abort:
+ mov r6, #5
+ b reset
+
+data_abort:
+ mov r6, #6
+ b reset
+
+not_used:
+ /* we *should* never reach this */
+ mov r6, #7
+ b reset
+
+irq:
+ mov r6, #8
+ b reset
+
+fiq:
+ mov r6, #9
+ b reset