| commit | 060f9bf57b1dc1f9260bc1b999d054141b87d7d2 | [log] [tgz] |
|---|---|---|
| author | Alexander Stein <alexanders83@web.de> | Fri Jul 24 09:22:11 2015 +0200 |
| committer | Tom Rini <trini@konsulko.com> | Wed Aug 12 20:47:41 2015 -0400 |
| tree | ac71ebcf77ce3b3c9e163542dc06d16e28fa6a64 | |
| parent | 2085ae74dee47ed3da63416aac0305936b43eeea [diff] |
ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>