Merge branch 'master' of git://git.denx.de/u-boot-i2c
* 'master' of git://git.denx.de/u-boot-i2c:
i2c:designware Turn off the ctrl when setting the speed
i2c: Add support for designware i2c controller
sh: i2c: Add support I2C controller of SH7734
diff --git a/MAINTAINERS b/MAINTAINERS
index 708ded7..e2441d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1191,6 +1191,7 @@
ADP-AG101 N1213 (AG101 SoC)
ADP-AG101P N1213 (AG101P XC5 FPGA)
+ ADP-AG102 N1213f (AG102 SoC with FPU)
#########################################################################
# OpenRISC Systems: #
diff --git a/Makefile b/Makefile
index cdd4294..023ea23 100644
--- a/Makefile
+++ b/Makefile
@@ -23,7 +23,7 @@
VERSION = 2012
PATCHLEVEL = 04
-SUBLEVEL =
+SUBLEVEL = 01
EXTRAVERSION =
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
diff --git a/README b/README
index 43074cf..f726303 100644
--- a/README
+++ b/README
@@ -814,7 +814,7 @@
CONFIG_CMD_TIME * run command and report execution time
CONFIG_CMD_USB * USB support
CONFIG_CMD_CDP * Cisco Discover Protocol support
- CONFIG_CMD_FSL * Microblaze FSL support
+ CONFIG_CMD_MFSL * Microblaze FSL support
EXAMPLE: If you want all functions except of network
diff --git a/arch/arm/cpu/armv7/omap-common/spl_nand.c b/arch/arm/cpu/armv7/omap-common/spl_nand.c
index 1295e88..8cf55c9 100644
--- a/arch/arm/cpu/armv7/omap-common/spl_nand.c
+++ b/arch/arm/cpu/armv7/omap-common/spl_nand.c
@@ -54,7 +54,7 @@
* load parameter image
* load to temp position since nand_spl_load_image reads
* a whole block which is typically larger than
- * CONFIG_CMD_SAVEBP_WRITE_SIZE therefore may overwrite
+ * CONFIG_CMD_SPL_WRITE_SIZE therefore may overwrite
* following sections like BSS
*/
nand_spl_load_image(CONFIG_CMD_SPL_NAND_OFS,
diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h
index 1a8de49..25cd833 100644
--- a/arch/blackfin/include/asm/config.h
+++ b/arch/blackfin/include/asm/config.h
@@ -109,14 +109,8 @@
#ifndef CONFIG_SYS_MALLOC_BASE
# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#endif
-#ifndef CONFIG_SYS_GBL_DATA_ADDR
-# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
-#endif
-#ifndef CONFIG_SYS_BD_INFO_ADDR
-# define CONFIG_SYS_BD_INFO_ADDR (CONFIG_SYS_GBL_DATA_ADDR - GENERATED_BD_INFO_SIZE)
-#endif
#ifndef CONFIG_STACKBASE
-# define CONFIG_STACKBASE (CONFIG_SYS_BD_INFO_ADDR - 4)
+# define CONFIG_STACKBASE (CONFIG_SYS_MALLOC_BASE - 4)
#endif
#ifndef CONFIG_SYS_MEMTEST_START
# define CONFIG_SYS_MEMTEST_START 0
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
index 67aa30f..973ea29 100644
--- a/arch/blackfin/include/asm/global_data.h
+++ b/arch/blackfin/include/asm/global_data.h
@@ -73,6 +73,6 @@
#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
-#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3")
+#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P3")
#endif
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index e3ee4cd..2d424a2 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -181,6 +181,46 @@
}
}
+static int global_board_data_init(void)
+{
+#ifndef CONFIG_SYS_GBL_DATA_ADDR
+# define CONFIG_SYS_GBL_DATA_ADDR 0
+#endif
+#ifndef CONFIG_SYS_BD_INFO_ADDR
+# define CONFIG_SYS_BD_INFO_ADDR 0
+#endif
+
+ bd_t *bd;
+
+ if (CONFIG_SYS_GBL_DATA_ADDR) {
+ gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
+ memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
+ } else {
+ static gd_t _bfin_gd;
+ gd = &_bfin_gd;
+ }
+
+ if (CONFIG_SYS_BD_INFO_ADDR) {
+ bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR);
+ memset(bd, 0, GENERATED_BD_INFO_SIZE);
+ } else {
+ static bd_t _bfin_bd;
+ bd = &_bfin_bd;
+ }
+ gd->bd = bd;
+
+ bd->bi_r_version = version_string;
+ bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
+ bd->bi_board_name = BFIN_BOARD_NAME;
+ bd->bi_vco = get_vco();
+ bd->bi_cclk = get_cclk();
+ bd->bi_sclk = get_sclk();
+ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+
+ return 0;
+}
+
/*
* All attempts to come up with a "common" initialization sequence
* that works for all boards and architectures failed: some of the
@@ -201,7 +241,6 @@
void board_init_f(ulong bootflag)
{
- bd_t *bd;
char buf[32];
#ifdef CONFIG_BOARD_EARLY_INIT_F
@@ -234,21 +273,8 @@
hang();
#endif
serial_early_puts("Init global data\n");
- gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
- memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
- bd = (bd_t *) (CONFIG_SYS_BD_INFO_ADDR);
- gd->bd = bd;
- memset((void *)bd, 0, GENERATED_BD_INFO_SIZE);
-
- bd->bi_r_version = version_string;
- bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
- bd->bi_board_name = BFIN_BOARD_NAME;
- bd->bi_vco = get_vco();
- bd->bi_cclk = get_cclk();
- bd->bi_sclk = get_sclk();
- bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
- bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+ global_board_data_init();
/* Initialize */
serial_early_puts("IRQ init\n");
@@ -276,7 +302,7 @@
if (CONFIG_MEM_SIZE) {
printf("RAM: ");
- print_size(bd->bi_memsize, "\n");
+ print_size(gd->bd->bi_memsize, "\n");
}
#if defined(CONFIG_POST)
diff --git a/arch/nds32/cpu/n1213/ag102/Makefile b/arch/nds32/cpu/n1213/ag102/Makefile
new file mode 100644
index 0000000..8716c4e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y := cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS += watchdog.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
new file mode 100644
index 0000000..4769a95
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
@@ -0,0 +1,54 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+ OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
+ OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
+#endif
+ BLANK();
+#ifdef CONFIG_FTAHBC020S
+ OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
+ OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
+#endif
+ BLANK();
+#ifdef CONFIG_ANDES_PCU
+ OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
+#endif
+ BLANK();
+#ifdef CONFIG_DWCDDR21MCTL
+ OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */
+ OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */
+ OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */
+ OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */
+ OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */
+ OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
+ OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
+ OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
+ OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
+ OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
+ OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
+ OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
+ OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
+ OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
+ OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
+ OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
+ OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
+ OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
+ OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
+#endif
+ return 0;
+}
diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c
new file mode 100644
index 0000000..ed88b52
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/cpu.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include <faraday/ftwdt010_wdt.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+#ifdef CONFIG_MMU
+ /* turn off I/D-cache */
+ icache_disable();
+ dcache_disable();
+
+ /* flush I/D-cache */
+ invalidate_icac();
+ invalidate_dcac();
+#endif
+
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+
+ /*
+ * reset to the base addr of andesboot.
+ * currently no ROM loader at addr 0.
+ * do not use reset_cpu(0);
+ */
+#ifdef CONFIG_FTWDT010_WATCHDOG
+ /*
+ * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
+ * automatic hardware reset when booting Linux.
+ * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
+ */
+ ftwdt010_wdt_reset();
+#endif /* CONFIG_FTWDT010_WATCHDOG */
+ hang();
+
+ /*NOTREACHED*/
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+ if (cache == ICACHE)
+ return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+ >> ICM_CFG_OFF_ISZ) - 1);
+ else
+ return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+ >> DCM_CFG_OFF_DSZ) - 1);
+}
+
+void dcache_flush_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(DCACHE);
+
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+ __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void icache_inval_range(unsigned long start, unsigned long end)
+{
+ unsigned long line_size;
+
+ line_size = CACHE_LINE_SIZE(ICACHE);
+ while (end > start) {
+ __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+ start += line_size;
+ }
+}
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+ dcache_flush_range(addr, addr + size);
+ icache_inval_range(addr, addr + size);
+}
+
+void icache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x01\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void icache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x01\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int icache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x01\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
+
+void dcache_enable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "ori $p0, $p0, 0x02\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+void dcache_disable(void)
+{
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "li $p1, ~0x02\n\t"
+ "and $p0, $p0, $p1\n\t"
+ "mtsr $p0, $mr8\n\t"
+ "isb\n\t"
+ );
+}
+
+int dcache_status(void)
+{
+ int ret;
+
+ __asm__ __volatile__ (
+ "mfsr $p0, $mr8\n\t"
+ "andi %0, $p0, 0x02\n\t"
+ : "=r" (ret)
+ :
+ : "memory"
+ );
+
+ return ret;
+}
diff --git a/arch/nds32/cpu/n1213/ag102/lowlevel_init.S b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S
new file mode 100644
index 0000000..d842afa
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S
@@ -0,0 +1,297 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.text
+
+#include <common.h>
+#include <config.h>
+
+#include <asm/macro.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * parameters for Synopsys DWC DDR2/DDR1 Memory Controller
+ */
+#define DDR2C_BASE_A (CONFIG_DWCDDR21MCTL_BASE)
+#define DDR2C_CCR_A (DDR2C_BASE_A + DWCDDR21MCTL_CCR)
+#define DDR2C_DCR_A (DDR2C_BASE_A + DWCDDR21MCTL_DCR)
+#define DDR2C_IOCR_A (DDR2C_BASE_A + DWCDDR21MCTL_IOCR)
+#define DDR2C_CSR_A (DDR2C_BASE_A + DWCDDR21MCTL_CSR)
+#define DDR2C_DRR_A (DDR2C_BASE_A + DWCDDR21MCTL_DRR)
+#define DDR2C_DLLCR0_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR0)
+#define DDR2C_DLLCR1_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR1)
+#define DDR2C_DLLCR2_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR2)
+#define DDR2C_DLLCR3_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR3)
+#define DDR2C_DLLCR4_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR4)
+#define DDR2C_DLLCR5_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR5)
+#define DDR2C_DLLCR6_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR6)
+#define DDR2C_DLLCR7_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR7)
+#define DDR2C_DLLCR8_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR8)
+#define DDR2C_DLLCR9_A (DDR2C_BASE_A + DWCDDR21MCTL_DLLCR9)
+#define DDR2C_RSLR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RSLR0)
+#define DDR2C_RDGR0_A (DDR2C_BASE_A + DWCDDR21MCTL_RDGR0)
+#define DDR2C_DTAR_A (DDR2C_BASE_A + DWCDDR21MCTL_DTAR)
+#define DDR2C_MR_A (DDR2C_BASE_A + DWCDDR21MCTL_MR)
+
+#define DDR2C_CCR_D CONFIG_SYS_DWCDDR21MCTL_CCR
+#define DDR2C_CCR_D2 CONFIG_SYS_DWCDDR21MCTL_CCR2
+#define DDR2C_DCR_D CONFIG_SYS_DWCDDR21MCTL_DCR
+#define DDR2C_IOCR_D CONFIG_SYS_DWCDDR21MCTL_IOCR
+#define DDR2C_CSR_D CONFIG_SYS_DWCDDR21MCTL_CSR
+#define DDR2C_DRR_D CONFIG_SYS_DWCDDR21MCTL_DRR
+#define DDR2C_RSLR0_D CONFIG_SYS_DWCDDR21MCTL_RSLR0
+#define DDR2C_RDGR0_D CONFIG_SYS_DWCDDR21MCTL_RDGR0
+#define DDR2C_DTAR_D CONFIG_SYS_DWCDDR21MCTL_DTAR
+#define DDR2C_MR_D CONFIG_SYS_DWCDDR21MCTL_MR
+
+#define DDR2C_DLLCR0_D CONFIG_SYS_DWCDDR21MCTL_DLLCR0 /* 0-9 are same */
+
+/*
+ * parameters for the ahbc controller
+ */
+#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
+#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
+
+#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
+
+/*
+ * parameters for the ANDES PCU controller
+ */
+#define PCU_PCS4_A (CONFIG_ANDES_PCU_BASE + ANDES_PCU_PCS4)
+#define PCU_PCS4_D CONFIG_SYS_ANDES_CPU_PCS4
+
+/*
+ * numeric 7 segment display
+ */
+.macro led, num
+ write32 CONFIG_DEBUG_LED, \num
+.endm
+
+/*
+ * Waiting for SDRAM to set up
+ */
+/*
+.macro wait_sdram
+ li $r0, DDR2C_CSR_A
+1:
+ lwi $r1, [$r0+FTSDMC021_CR2]
+ bnez $r1, 1b
+.endm
+*/
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+.globl lowlevel_init
+lowlevel_init:
+ move $r10, $lp
+
+ /* U200 */
+! led 0x00
+! jal scale_to_500mhz
+
+ led 0x10
+ jal mem_init
+
+ led 0x20
+ jal remap
+
+ led 0x30
+ ret $r10
+
+scale_to_500mhz:
+ move $r11, $lp
+
+ /*
+ * scale to 500Mhz
+ */
+ led 0x01
+ write32 PCU_PCS4_A, 0x1102000f ! save data to PCS4
+
+ move $lp, $r11
+ ret
+
+mem_init:
+ move $r11, $lp
+
+ /*
+ * config AHB Controller
+ */
+ led 0x12
+ write32 AHBC_BSR6_A, AHBC_BSR6_D
+
+ /*
+ * config Synopsys DWC DDR2/DDR1 Memory Controller
+ */
+ddr2c_init:
+set_dcr:
+ led 0x14
+ write32 DDR2C_DCR_A, DDR2C_DCR_D ! 0x000020d4
+
+auto_sizing:
+ /*
+ * ebios: $r10->$r7, $r11->$r8, $r12->$r9, $r13->$r12, $r14->$r13
+ */
+set_iocr:
+ led 0x19
+ write32 DDR2C_IOCR_A, DDR2C_IOCR_D
+set_drr:
+ led 0x16
+ write32 DDR2C_DRR_A, DDR2C_DRR_D ! 0x00034812
+set_dllcr:
+ led 0x18
+ write32 DDR2C_DLLCR0_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR1_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR2_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR3_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR4_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR5_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR6_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR7_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR8_A, DDR2C_DLLCR0_D
+ write32 DDR2C_DLLCR9_A, DDR2C_DLLCR0_D
+set_rslr0:
+ write32 DDR2C_RSLR0_A, DDR2C_RSLR0_D ! 0x00000040
+set_rdgr0:
+ write32 DDR2C_RDGR0_A, DDR2C_RDGR0_D ! 0x000055cf
+set_dtar:
+ led 0x15
+ write32 DDR2C_DTAR_A, DDR2C_DTAR_D ! 0x00100000
+set_mode:
+ led 0x17
+ write32 DDR2C_MR_A, DDR2C_MR_D ! 0x00000852
+set_ccr:
+ write32 DDR2C_CCR_A, DDR2C_CCR_D
+
+#ifdef TRIGGER_INIT:
+trigger_init:
+ write32 DDR2C_CCR_A, DDR2C_CCR_D ! 0x80020000
+
+ /* Wait for ddr init state to be set */
+ msync ALL
+ isb
+
+ /* Wait until the config initialization is finish */
+1:
+ la $r4, DDR2C_CSR_A
+ lwi $r5, [$r4]
+ srli $r5, $r5, 23
+ bnez $r5, 1b
+#endif
+
+data_training:
+! write32 DDR2C_CCR_A, DDR2C_CCR_D2 ! 0x40020004
+
+ /* Wait for ddr init state to be set */
+ msync ALL
+ isb
+
+ /* wait until the ddr data trainning is complete */
+1:
+ la $r4, DDR2C_CSR_A
+ lwi $r5, [$r4]
+ srli $r6, $r5, 23
+ bnez $r6, 1b
+
+ lwi $r1, [$r4]
+ srli $r6, $r5, 20
+ li $r5, 0x00ffffff
+ swi $r1, [$r4]
+ bnez $r6, ddr2c_init
+
+ led 0x1a
+ move $lp, $r11
+ ret
+
+remap:
+ move $r11, $lp
+#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
+ bal 2f
+relo_base:
+ move $r0, $lp
+#else
+relo_base:
+ mfusr $r0, $pc
+#endif /* __NDS32_N1213_43U1H__ */
+
+ /*
+ * Remapping
+ */
+#ifdef CONFIG_MEM_REMAP
+ /*
+ * Copy ROM code to SDRAM base for memory remap layout.
+ * This is not the real relocation, the real relocation is the function
+ * relocate_code() is start.S which supports the systems is memory
+ * remapped or not.
+ */
+ /*
+ * Doing memory remap is essential for preparing some non-OS or RTOS
+ * applications.
+ *
+ * This is also a must on ADP-AG101 board.
+ * The reason is because the ROM/FLASH circuit on PCB board.
+ * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
+ * ROM/FLASH is used to boot.
+ *
+ * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
+ * and the FLASH is connected to BANK1.
+ * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
+ * and the FLASH is connected to BANK0.
+ * It will occur problem when doing flash probing if the flash is at
+ * BANK0 (0x00000000) while memory remapping was skipped.
+ *
+ * Other board like ADP-AG101P may not enable this since there is only
+ * a FLASH connected to bank0.
+ */
+ led 0x21
+ li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
+ li $r5, 0x0
+ la $r1, relo_base /* get $pc or $lp */
+ sub $r2, $r0, $r1
+ sethi $r6, hi20(_end)
+ ori $r6, $r6, lo12(_end)
+ add $r6, $r6, $r2
+1:
+ lwi.p $r7, [$r5], #4
+ swi.p $r7, [$r4], #4
+ blt $r5, $r6, 1b
+
+ /* set remap bit */
+ /*
+ * MEM remap bit is operational
+ * - use it to map writeable memory at 0x00000000, in place of flash
+ * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
+ * - after remap: flash/rom 0x80000000, sdram: 0x00000000
+ */
+ led 0x2c
+ setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
+
+#endif /* #ifdef CONFIG_MEM_REMAP */
+ move $lp, $r11
+2:
+ ret
+
+.globl show_led
+show_led:
+ li $r8, (CONFIG_DEBUG_LED)
+ swi $r7, [$r8]
+ ret
+#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/nds32/cpu/n1213/ag102/timer.c b/arch/nds32/cpu/n1213/ag102/timer.c
new file mode 100644
index 0000000..caa36b8
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/timer.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/fttmr010.h>
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+ unsigned int cr;
+
+ debug("%s()\n", __func__);
+
+ /* disable timers */
+ writel(0, &tmr->cr);
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ /* use 32768Hz oscillator for RTC, WDT, TIMER */
+ ftpmu010_32768osc_enable();
+#endif
+
+ /* setup timer */
+ writel(TIMER_LOAD_VAL, &tmr->timer3_load);
+ writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
+ writel(0, &tmr->timer3_match1);
+ writel(0, &tmr->timer3_match2);
+
+ /* we don't want timer to issue interrupts */
+ writel(FTTMR010_TM3_MATCH1 |
+ FTTMR010_TM3_MATCH2 |
+ FTTMR010_TM3_OVERFLOW,
+ &tmr->interrupt_mask);
+
+ cr = readl(&tmr->cr);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ cr |= FTTMR010_TM3_CLOCK; /* use external clock */
+#endif
+ cr |= FTTMR010_TM3_ENABLE;
+ writel(cr, &tmr->cr);
+
+ /* init the timestamp and lastdec value */
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * reset time
+ */
+void reset_timer_masked(void)
+{
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* capure current decrementer value time */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ lastdec = readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2);
+#endif
+ timestamp = 0; /* start "advancing" time stamp from 0 */
+
+ debug("%s(): lastdec = %lx\n", __func__, lastdec);
+}
+
+void reset_timer(void)
+{
+ debug("%s()\n", __func__);
+ reset_timer_masked();
+}
+
+/*
+ * return timer ticks
+ */
+ulong get_timer_masked(void)
+{
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+ /* current tick value */
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+#else
+ ulong now = readl(&tmr->timer3_counter) / \
+ (CONFIG_SYS_CLK_FREQ / 2 / 1024);
+#endif
+
+ debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
+
+ if (lastdec >= now) {
+ /*
+ * normal mode (non roll)
+ * move stamp fordward with absoulte diff ticks
+ */
+ timestamp += lastdec - now;
+ } else {
+ /*
+ * we have overflow of the count down timer
+ *
+ * nts = ts + ld + (TLV - now)
+ * ts=old stamp, ld=time that passed before passing through -1
+ * (TLV-now) amount of time after passing though -1
+ * nts = new "advancing time stamp"...it could also roll and
+ * cause problems.
+ */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ }
+
+ lastdec = now;
+
+ debug("%s() returns %lx\n", __func__, timestamp);
+
+ return timestamp;
+}
+
+/*
+ * return difference between timer ticks and base
+ */
+ulong get_timer(ulong base)
+{
+ debug("%s(%lx)\n", __func__, base);
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+ debug("%s(%lx)\n", __func__, t);
+ timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void __udelay(unsigned long usec)
+{
+ struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
+
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+#else
+ long tmo = usec * ((CONFIG_SYS_CLK_FREQ / 2) / 1000) / 1000;
+#endif
+ unsigned long now, last = readl(&tmr->timer3_counter);
+
+ debug("%s(%lu)\n", __func__, usec);
+ while (tmo > 0) {
+ now = readl(&tmr->timer3_counter);
+ if (now > last) /* count down timer overflow */
+ tmo -= TIMER_LOAD_VAL + last - now;
+ else
+ tmo -= last - now;
+ last = now;
+ }
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ debug("%s()\n", __func__);
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ debug("%s()\n", __func__);
+#ifdef CONFIG_FTTMR010_EXT_CLK
+ return CONFIG_SYS_HZ;
+#else
+ return CONFIG_SYS_CLK_FREQ;
+#endif
+}
diff --git a/arch/nds32/cpu/n1213/ag102/watchdog.S b/arch/nds32/cpu/n1213/ag102/watchdog.S
new file mode 100644
index 0000000..56cecda
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/watchdog.S
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch-ag102/ag102.h>
+#include <linux/linkage.h>
+
+.text
+
+#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+ENTRY(turnoff_watchdog)
+
+#define WD_CR 0xC
+#define WD_ENABLE 0x1
+
+ ! Turn off the watchdog, according to Faraday FTWDT010 spec
+ li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
+ lwi $p1, [$p0] ! Get the config of WD
+ andi $p1, $p1, 0x1f ! Wipe out useless bits
+ li $r0, ~WD_ENABLE
+ and $p1, $p1, $r0 ! Set WD disable
+ sw $p1, [$p0] ! Write back to WD CR
+
+ ! Disable Interrupts by clear GIE in $PSW reg
+ setgie.d
+
+ ret
+
+ENDPROC(turnoff_watchdog)
+#endif
diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h
new file mode 100644
index 0000000..a12a8c5
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG102_H
+#define __AG102_H
+
+/*
+ * Hardware register bases
+ */
+
+/* PCI Controller */
+#define CONFIG_FTPCI100_BASE 0x90000000
+/* LPC Controller */
+#define CONFIG_LPC_IO_BASE 0x90100000
+/* LPC Controller */
+#define CONFIG_LPC_BASE 0x90200000
+
+/* NDS32 Data Local Memory 01 */
+#define CONFIG_NDS_DLM1_BASE 0x90300000
+/* NDS32 Data Local Memory 02 */
+#define CONFIG_NDS_DLM2_BASE 0x90400000
+
+/* Synopsys DWC DDR2/1 Controller */
+#define CONFIG_DWCDDR21MCTL_BASE 0x90500000
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE 0x90600000
+/* FTIDE020_S IDE (ATA) Controller */
+#define CONFIG_FTIDE020S_BASE 0x90700000
+/* USB OTG Controller */
+#define CONFIG_FZOTG266HD0A_BASE 0x90800000
+/* Andes L2 Cache Controller */
+#define CONFIG_NCEL2C100_BASE 0x90900000
+/* XGI XG22 GPU */
+#define CONFIG_XGI_XG22_BASE 0x90A00000
+/* GMAC Ethernet Controller */
+#define CONFIG_FTGMAC100_BASE 0x90B00000
+/* AHB Controller */
+#define CONFIG_FTAHBC020S_BASE 0x90C00000
+/* AHB-to-APB Bridge Controller */
+#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000
+/* External AHB2AHB Controller */
+#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000
+/* Andes Multi-core Interrupt Controller */
+#define CONFIG_NCEMIC100_BASE 0x90F00000
+
+/*
+ * APB Device definitions
+ */
+/* Compat Flash Controller */
+#define CONFIG_FTCFC010_BASE 0x94000000
+/* APB - SSP (SPI) (without AC97) Controller */
+#define CONFIG_FTSSP010_01_BASE 0x94100000
+/* UART1 - APB STUART Controller (UART0 in Linux) */
+#define CONFIG_FTUART010_01_BASE 0x94200000
+/* FTSDC010 SD Controller */
+#define CONFIG_FTSDC010_BASE 0x94400000
+/* APB - SSP with HDA/AC97 Controller */
+#define CONFIG_FTSSP010_02_BASE 0x94500000
+/* UART2 - APB STUART Controller (UART1 in Linux) */
+#define CONFIG_FTUART010_02_BASE 0x94600000
+/* PCU Controller */
+#define CONFIG_ANDES_PCU_BASE 0x94800000
+/* FTTMR010 Timer */
+#define CONFIG_FTTMR010_BASE 0x94900000
+/* Watch Dog Controller */
+#define CONFIG_FTWDT010_BASE 0x94A00000
+/* FTRTC010 Real Time Clock */
+#define CONFIG_FTRTC010_BASE 0x98B00000
+/* GPIO Controller */
+#define CONFIG_FTGPIO010_BASE 0x94C00000
+/* I2C Controller */
+#define CONFIG_FTIIC010_BASE 0x94E00000
+/* PWM - Pulse Width Modulator Controller */
+#define CONFIG_FTPWM010_BASE 0x94F00000
+
+/* Debug LED */
+#define CONFIG_DEBUG_LED 0x902FFFFC
+/* Power Management Unit */
+#define CONFIG_FTPMU010_BASE 0x98100000
+
+#endif /* __AG102_H */
diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h
index 7b52b98..259e4e7 100644
--- a/arch/nds32/include/asm/mach-types.h
+++ b/arch/nds32/include/asm/mach-types.h
@@ -40,4 +40,18 @@
# define machine_is_adpag101p() (1)
#endif
+#define MACH_TYPE_ADPAG102 2
+
+#ifdef CONFIG_ARCH_ADPAG102
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ADPAG102
+# endif
+# define machine_is_adpag102() (machine_arch_type == MACH_TYPE_ADPAG102)
+#else
+# define machine_is_adpag102() (2)
+#endif
+
#endif /* __ASM_NDS32_MACH_TYPE_H */
diff --git a/board/AndesTech/adp-ag102/Makefile b/board/AndesTech/adp-ag102/Makefile
new file mode 100644
index 0000000..1cbf2d4
--- /dev/null
+++ b/board/AndesTech/adp-ag102/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := adp-ag102.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag102/adp-ag102.c b/board/AndesTech/adp-ag102/adp-ag102.c
new file mode 100644
index 0000000..5a25632
--- /dev/null
+++ b/board/AndesTech/adp-ag102/adp-ag102.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+ * refer to BOOT_PARAMETER_PA_BASE within
+ * "linux/arch/nds32/include/asm/misc_spec.h"
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG102;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ ftsmc020_init(); /* initialize Flash */
+#endif /* CONFIG_SYS_NO_FLASH */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftgmac100_initialize(bd);
+}
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+void pci_init_board(void)
+{
+ /* should be pci_ftpci100_init() */
+ extern void pci_ftpci_init();
+
+ pci_ftpci_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ ftsdc010_mmc_init(0);
+ return 0;
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 3cf75c3..3b8be87 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -370,6 +370,7 @@
qi_lb60 mips xburst qi_lb60 qi
adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101
adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101
+adp-ag102 nds32 n1213 adp-ag102 AndesTech ag102
nios2-generic nios2 nios2 nios2-generic altera
PCI5441 nios2 nios2 pci5441 psyent
PK1C20 nios2 nios2 pk1c20 psyent
diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index bae630d..0fd3a6c 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -191,7 +191,7 @@
loff_t *off, loff_t *size)
{
int ret;
- loff_t maxsize;
+ loff_t maxsize = 0;
if (argc == 0) {
*off = 0;
diff --git a/doc/README.ag102 b/doc/README.ag102
new file mode 100644
index 0000000..7d142a7
--- /dev/null
+++ b/doc/README.ag102
@@ -0,0 +1,36 @@
+Andes Technology SoC AG102
+==========================
+
+AG102 is the second SoC produced by Andes Technology using N1213 CPU core
+with FPU and DDR contoller support.
+AG102 has integrated both AHB and APB bus and many periphals for application
+and product development.
+
+ADP-AG102
+=========
+
+ADP-AG102 is the SoC with AG102 hardcore CPU.
+
+Configurations
+==============
+
+CONFIG_MEM_REMAP:
+ Doing memory remap is essential for preparing some non-OS or RTOS
+ applications.
+
+CONFIG_SKIP_LOWLEVEL_INIT:
+ If you want to boot this system from SPI ROM and bypass e-bios (the
+ other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
+ in "include/configs/adp-ag102.h".
+
+Build and boot steps
+====================
+
+build:
+1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
+2. Use `make adp-ag102` in u-boot root to build the image.
+
+Burn u-boot to SPI ROM:
+====================
+
+This section will be added later.
diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c
index 08fc5c1..8d59d46 100644
--- a/drivers/mmc/bfin_sdh.c
+++ b/drivers/mmc/bfin_sdh.c
@@ -256,7 +256,6 @@
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->f_max = get_sclk();
mmc->f_min = mmc->f_max >> 9;
- mmc->block_dev.part_type = PART_TYPE_DOS;
mmc->b_max = 0;
diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h
index 2c6b829..55f4f7a 100644
--- a/include/config_cmd_all.h
+++ b/include/config_cmd_all.h
@@ -15,7 +15,6 @@
#define CONFIG_CMD_AMBAPP /* AMBA Plug & Play Bus print utility */
#define CONFIG_CMD_ASKENV /* ask for env variable */
-#define CONFIG_CMD_AT91_SPIMUX /* AT91 MMC/SPI Mux Support */
#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */
#define CONFIG_CMD_BMP /* BMP support */
diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h
index 01597b9..f08d78b 100644
--- a/include/configs/HWW1U1A.h
+++ b/include/configs/HWW1U1A.h
@@ -422,7 +422,7 @@
#define CONFIG_MD5
#define CONFIG_SHA1
#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_SHA1
+#define CONFIG_CMD_SHA1SUM
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_SETEXPR
diff --git a/include/configs/MBX.h b/include/configs/MBX.h
index cb5b023..79780bd 100644
--- a/include/configs/MBX.h
+++ b/include/configs/MBX.h
@@ -87,7 +87,6 @@
* Command line configuration.
*/
#define CONFIG_CMD_NET
-#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_IDE
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index 619a800..84ba78f 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -38,7 +38,6 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS
-#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SAVEENV
diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h
new file mode 100644
index 0000000..a4628e4
--- /dev/null
+++ b/include/configs/adp-ag102.h
@@ -0,0 +1,375 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag102.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG102
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x04200000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#endif
+
+/*
+ * Timer
+ */
+
+/*
+ * According to the discussion in u-boot mailing list before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_SYS_CLK_FREQ (66000000 * 2)
+#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ (5*1000000)
+#define OSC_CLK (2*OSC_5MHZ)
+#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_01_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK 33000000 /* AG102 */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_MAX_ADDR 32 /* this comes from <linux/phy.h> */
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_FTGMAC100
+#define CONFIG_FTGMAC100_EGIGA
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER 1
+#define CONFIG_FTSDC010_SDIO
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+/*
+ * PCI
+ */
+#define CONFIG_PCI
+#define CONFIG_FTPCI100
+#define CONFIG_FTPCI100_MEM_BASE 0xa0000000
+#define CONFIG_FTPCI100_IO_SIZE FTPCI100_BASE_IO_SIZE(256) /* 256M */
+#define CONFIG_FTPCI100_MEM_SIZE FTPCI100_MEM_SIZE(128) /* 128M */
+#define CONFIG_FTPCI100_MEM_BASE_SIZE1 0x50
+
+#define CONFIG_PCI_MEM_BUS 0xa0000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x01000000 /* 256M */
+
+#define CONFIG_PCI_IO_BUS 0x90000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x00100000 /* 1M */
+
+/*
+ * USB
+ */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#if defined(CONFIG_FTPCI100)
+#define __io /* enable outl & inl */
+#define CONFIG_CMD_USB
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_PCI_EHCI_DEVICE 0
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_PREBOOT "usb start;"
+#endif /* #if defiend(CONFIG_FTPCI100) */
+#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
+
+/*
+ * IDE/ATA stuff
+ */
+#define __io
+#define CONFIG_IDE_AHB
+#define CONFIG_IDE_FTIDE020
+
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+#define CONFIG_IDE_RESET 1 /* reset for ide supported */
+#define CONFIG_IDE_PREINIT 1 /* preinit for ide */
+
+/* max: 2 IDE busses */
+#define CONFIG_SYS_IDE_MAXBUS 1 /* origin: 2 */
+/* max: 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 1 /* origin: (MAXBUS * 2) */
+
+#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_FTIDE020S_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* for normal regs access */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* for alternate regs */
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*
+ * size in bytes reserved for initial data
+*/
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+ (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+ FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PCU Power Control Unit configuration
+ */
+#define CONFIG_ANDES_PCU
+
+#ifdef CONFIG_ANDES_PCU
+#include <andestech/andes_pcu.h>
+
+#endif
+
+/*
+ * DDR DRAM controller configuration
+ */
+#define CONFIG_DWCDDR21MCTL
+
+#ifdef CONFIG_DWCDDR21MCTL
+#include <synopsys/dwcddr21mctl.h>
+/* DCR:
+ * 2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
+ * 1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
+ * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
+ * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
+ * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
+ */
+#define CONFIG_SYS_DWCDDR21MCTL_CCR 0x00020004
+#define CONFIG_SYS_DWCDDR21MCTL_CCR2 (DWCDDR21MCTL_CCR_DTT(0x1) | \
+ DWCDDR21MCTL_CCR_DFTLM(0x4) | \
+ DWCDDR21MCTL_CCR_HOSTEN(0x1))
+
+/* 0x04: 0x000020d4 */
+#define CONFIG_SYS_DWCDDR21MCTL_DCR 0x000020ca
+
+/* 0x08: 0x0000000f */
+#define CONFIG_SYS_DWCDDR21MCTL_IOCR 0x0000000f
+
+/* 0x10: 0x00034812 */
+#define CONFIG_SYS_DWCDDR21MCTL_DRR (DWCDDR21MCTL_DRR_TRFC(0x12) | \
+ DWCDDR21MCTL_DRR_TRFPRD(0x0348))
+/* 0x24 */
+#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0 DWCDDR21MCTL_DLLCR_PHASE(0x0)
+
+/* 0x4c: 0x00000040 */
+#define CONFIG_SYS_DWCDDR21MCTL_RSLR0 0x00000040
+
+/* 0x5c: 0x000055CF */
+#define CONFIG_SYS_DWCDDR21MCTL_RDGR0 0x000055cf
+
+/* 0xa4: 0x00100000 */
+#define CONFIG_SYS_DWCDDR21MCTL_DTAR (DWCDDR21MCTL_DTAR_DTBANK(0x0) | \
+ DWCDDR21MCTL_DTAR_DTROW(0x0100) | \
+ DWCDDR21MCTL_DTAR_DTCOL(0x0))
+/* 0x1f0: 0x00000852 */
+#define CONFIG_SYS_DWCDDR21MCTL_MR (DWCDDR21MCTL_MR_WR(0x4) | \
+ DWCDDR21MCTL_MR_CL(0x5) | \
+ DWCDDR21MCTL_MR_BL(0x2))
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT 0x80000000 /* SDRAM Bank #1 before remap*/
+#endif
+#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE 0x10000000 /* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+ GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+ GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk
+ * Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x0CF00000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 4096
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 6a02188..159857d 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -107,7 +107,6 @@
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_PING
diff --git a/include/configs/debris.h b/include/configs/debris.h
index 60c7c40..303630d 100644
--- a/include/configs/debris.h
+++ b/include/configs/debris.h
@@ -148,7 +148,7 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_KGBD
+#define CONFIG_CMD_KGDB
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index d517334..1f66023 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -119,7 +119,6 @@
#ifdef CONFIG_VIDEO
#define CONFIG_CMD_BMP
#endif
-#define CONFIG_CMD_DFL
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h
index f19360d..221d3e0 100644
--- a/include/configs/ep8260.h
+++ b/include/configs/ep8260.h
@@ -325,7 +325,6 @@
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SNTP
-#undef CONFIG_CMD_DCR
#undef CONFIG_CMD_XIMG
/* Where do the internal registers live? */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 462cc7e..efff309 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -70,7 +70,6 @@
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_I2C
-#define CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#define CONFIG_CMD_USB
#define CONFIG_CMD_EXT2
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
index f72ee02..d644fea 100644
--- a/include/configs/jadecpu.h
+++ b/include/configs/jadecpu.h
@@ -130,7 +130,6 @@
#undef CONFIG_CMD_XIMG
#define CONFIG_CMD_BMP
-#define CONFIG_CMD_CAN
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 621dbb8..d505a41 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -447,7 +447,6 @@
*/
#define CONFIG_CMD_CHIP_CONFIG
#define CONFIG_CMD_DATE
-#define CONFIG_CMD_LOG
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index a6f2864..68215fd 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -435,7 +435,6 @@
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOG
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index fcc789d..6c1b136 100644
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -252,7 +252,6 @@
*/
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
-#define CONFIG_CMD_LOG
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index 7cf641f..f110490 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -35,7 +35,6 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
-#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_SAVEENV
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index 03f52f3..52e15cc 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -38,7 +38,6 @@
*/
/*#include <config_cmd_default.h>*/
-#define CONFIG_CMD_DFL
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_SAVEENV
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index 01360f6..4ac17cc 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -122,7 +122,7 @@
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SETECPR /* Evaluate expressions */
+#define CONFIG_CMD_SETEXPR /* Evaluate expressions */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h
index dc5ec3a..5d0c385 100644
--- a/include/configs/quad100hd.h
+++ b/include/configs/quad100hd.h
@@ -69,7 +69,6 @@
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_IRQ
#define CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_LOG
#undef CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#undef CONFIG_CMD_PING
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index 0ce3fa8..9cdfc14 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -15,7 +15,6 @@
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_DFL
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_PCI
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 73d2a87..708bff7 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -41,7 +41,6 @@
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS
-#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SF
#define CONFIG_CMD_RUN
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index 1e71bcc..9c32bfc 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -37,7 +37,6 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS
-#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVEENV
diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h
index 4747fbd..95028de 100644
--- a/include/configs/u8500_href.h
+++ b/include/configs/u8500_href.h
@@ -95,7 +95,6 @@
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EMMC
#define CONFIG_CMD_SOURCE
#define CONFIG_CMD_I2C
diff --git a/include/configs/zeus.h b/include/configs/zeus.h
index 63279b0..2556e3b 100644
--- a/include/configs/zeus.h
+++ b/include/configs/zeus.h
@@ -78,7 +78,6 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOG
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h
index 08924cc..e09c16a 100644
--- a/include/u-boot/md5.h
+++ b/include/u-boot/md5.h
@@ -11,7 +11,10 @@
struct MD5Context {
__u32 buf[4];
__u32 bits[2];
- unsigned char in[64];
+ union {
+ unsigned char in[64];
+ __u32 in32[16];
+ };
};
/*
diff --git a/lib/md5.c b/lib/md5.c
index 81a09e3..2ae4a06 100644
--- a/lib/md5.c
+++ b/lib/md5.c
@@ -153,8 +153,8 @@
byteReverse(ctx->in, 14);
/* Append length in bits and transform */
- ((__u32 *) ctx->in)[14] = ctx->bits[0];
- ((__u32 *) ctx->in)[15] = ctx->bits[1];
+ ctx->in32[14] = ctx->bits[0];
+ ctx->in32[15] = ctx->bits[1];
MD5Transform(ctx->buf, (__u32 *) ctx->in);
byteReverse((unsigned char *) ctx->buf, 4);
diff --git a/tools/patman/README b/tools/patman/README
index 587c97f..7ba9e80 100644
--- a/tools/patman/README
+++ b/tools/patman/README
@@ -93,17 +93,17 @@
First do a dry run:
-$ ./tools/scripts/patman/patman -n
+$ ./tools/patman/patman -n
If it can't detect the upstream branch, try telling it how many patches
there are in your series:
-$ ./tools/scripts/patman/patman -n -c5
+$ ./tools/patman/patman -n -c5
This will create patch files in your current directory and tell you who
it is thinking of sending them to. Take a look at the patch files.
-$ ./tools/scripts/patman/patman -n -c5 -s1
+$ ./tools/patman/patman -n -c5 -s1
Similar to the above, but skip the first commit and take the next 5. This
is useful if your top commit is for setting up testing.
@@ -197,7 +197,7 @@
Where Patches Are Sent
======================
-Once the patches are created, patman sends them using gti send-email. The
+Once the patches are created, patman sends them using git send-email. The
whole series is sent to the recipients in Series-to: and Series-cc.
You can Cc individual patches to other people with the Cc: tag. Tags in the
subject are also picked up to Cc patches. For example, a commit like this: