commit 028dbb8db1d18c5835ab34659f9ef7a516571524
author Ruchika Gupta <ruchika.gupta@freescale.com> Tue Sep 09 11:50:31 2014 +0530
committer York Sun <yorksun@freescale.com> Thu Oct 16 14:16:50 2014 -0700
tree b6c94157e8a8483a025b2ec4591df115422fe3ae
parent 48ef0d2a1002d3da0bf7ed13d0959bcbf782c792

fsl_sec : Change accessor function to take care of endianness

SEC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of SEC IP.

So update acessor functions with common SEC acessor functions to take care
both type of endianness.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

arch/powerpc/cpu/mpc85xx/cpu_init.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 5bfab70..bf9fbbf 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -803,7 +803,7 @@
 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 #define MCFGR_AXIPIPE 0x000000f0
 	if (IS_SVR_REV(svr, 1, 0))
-		clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
+		sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871

arch/powerpc/cpu/mpc85xx/fdt.c

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 3222e26..d4c3d9d 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -714,7 +714,7 @@
 		ccsr_sec_t __iomem *sec;
 
 		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
-		fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms));
+		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 	}
 #endif
 

arch/powerpc/cpu/mpc85xx/liodn.c

diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 19e130e..7a2d4be4 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -66,12 +66,12 @@
 		return;
 
 	/* QILCR[QSLOM] */
-	out_be32(&sec->qilcr_ms, 0x3ff<<16);
+	sec_out32(&sec->qilcr_ms, 0x3ff<<16);
 
 	base = (liodn_bases[FSL_HW_PORTAL_SEC].id[0] << 16) |
 		liodn_bases[FSL_HW_PORTAL_SEC].id[1];
 
-	out_be32(&sec->qilcr_ls, base);
+	sec_out32(&sec->qilcr_ls, base);
 }
 
 #ifdef CONFIG_SYS_DPAA_FMAN

arch/powerpc/cpu/mpc8xxx/fdt.c

diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 4cec5e1..c6b4d95 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -287,8 +287,8 @@
 	};
 
 	ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
-	u32 secvid_ms = in_be32(&sec->secvid_ms);
-	u32 ccbvid = in_be32(&sec->ccbvid);
+	u32 secvid_ms = sec_in32(&sec->secvid_ms);
+	u32 ccbvid = sec_in32(&sec->ccbvid);
 	u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
 				SEC_SECVID_MS_IPID_SHIFT;
 	u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>