clearfog: Clarify what's going on with the SPI NOR
Yup, it's the SPI master not initializing all HW CS pins properly (and
the same for the GPIO CS pins as well).
Change-Id: I4c6e0922e50e2f0c8e717a64fc2e6ca7bf6c8525
diff --git a/board/czechlight/clearfog/czechlight-clearfog.dts b/board/czechlight/clearfog/czechlight-clearfog.dts
index 296600e..8e4794a 100644
--- a/board/czechlight/clearfog/czechlight-clearfog.dts
+++ b/board/czechlight/clearfog/czechlight-clearfog.dts
@@ -2,10 +2,7 @@
&w25q32 {
status = "okay";
- /* The chip itself is rated up to 50MHz for regular reads, 60MHz for
- * all other transactions, but somehow the mere presence of the
- * MAX14830 EV board breaks these transfers. Changing the speed all the
- * way down to 100kHz doesn't help. */
+ /* FIXME: need to ensure that CS2 is high when probing for this... */
};
/ {