tree 2004076eb5ac72521a68f3d1e44c13437d77b7c2
parent 788e09c72dada8ba2c803636cbe5663627a61e51
author Jan Kundrát <jan.kundrat@cesnet.cz> 1705009312 +0100
committer Jan Kundrát <jan.kundrat@cesnet.cz> 1705062470 +0100

sync cla-sysrepo

This detects some silent data corruption over UARTs when the HW RX FIFO
overruns. My working theory is that this is related to some excessive
CPU load, but I have no data for that (and `perf` is still hosed).

Change-Id: I8fdb4fee60e65daf6756e72ad2d85fd62216bae5
Depends-on: https://gerrit.cesnet.cz/c/CzechLight/cla-sysrepo/+/6800