| commit | b1066e39fe136c4996f7d13b6003a958c1ea40a2 | [log] [tgz] |
|---|---|---|
| author | Jan Kundrát <jan.kundrat@cesnet.cz> | Thu Jan 11 22:41:52 2024 +0100 |
| committer | Jan Kundrát <jan.kundrat@cesnet.cz> | Fri Jan 12 13:27:50 2024 +0100 |
| tree | 2004076eb5ac72521a68f3d1e44c13437d77b7c2 | |
| parent | 788e09c72dada8ba2c803636cbe5663627a61e51 [diff] |
sync cla-sysrepo This detects some silent data corruption over UARTs when the HW RX FIFO overruns. My working theory is that this is related to some excessive CPU load, but I have no data for that (and `perf` is still hosed). Change-Id: I8fdb4fee60e65daf6756e72ad2d85fd62216bae5 Depends-on: https://gerrit.cesnet.cz/c/CzechLight/cla-sysrepo/+/6800
diff --git a/submodules/cla-sysrepo b/submodules/cla-sysrepo index 9039a52..4f4c472 160000 --- a/submodules/cla-sysrepo +++ b/submodules/cla-sysrepo
@@ -1 +1 @@ -Subproject commit 9039a526b5ff056de353830f54ac0a6327b11d0b +Subproject commit 4f4c4726b654e6a5dea572ff31dd622dba62b4ed