tree 1b5c72d3e8c13b4a736fe8d1215d444f869a54fb
parent bb4435a1ddffb4e8a7d564d9e4fb854b24ffa8b9
author Jan Kundrát <jan.kundrat@cesnet.cz> 1519658827 +0100
committer Jan Kundrát <jan.kundrat@cesnet.cz> 1519665342 +0100

clearfog: An inverter for OCM's SPI clock

It turned out that the spi-orion SPI master (perhaps the silicon, maybe
the driver, maybe the docs, but who cares) has troubles with transfers
which alternate CPOL=0 and CPOL=1. SOmetimes the changes only take
effect on the *next* transfer. This meant that we ended up with
addressing the OCM with CPOL=0 (wrong) and the GPIO expander with CPOL=1
(wrong as well). Given that we need a buffer on the SPI_CLK line to
ensure that anny attached crap doesn't pull it up, it's very easy to
just add a simple inverter gate. I used one NOR from a TI 74AHC02.

Change-Id: Ic78a0237c3e705fb8c9b4d66802fb64639ad1906