clearfog: An inverter for OCM's SPI clock
It turned out that the spi-orion SPI master (perhaps the silicon, maybe
the driver, maybe the docs, but who cares) has troubles with transfers
which alternate CPOL=0 and CPOL=1. SOmetimes the changes only take
effect on the *next* transfer. This meant that we ended up with
addressing the OCM with CPOL=0 (wrong) and the GPIO expander with CPOL=1
(wrong as well). Given that we need a buffer on the SPI_CLK line to
ensure that anny attached crap doesn't pull it up, it's very easy to
just add a simple inverter gate. I used one NOR from a TI 74AHC02.
Change-Id: Ic78a0237c3e705fb8c9b4d66802fb64639ad1906
diff --git a/board/czechlight/clearfog/czechlight-clearfog.dts b/board/czechlight/clearfog/czechlight-clearfog.dts
index 8e4794a..1d9ad74 100644
--- a/board/czechlight/clearfog/czechlight-clearfog.dts
+++ b/board/czechlight/clearfog/czechlight-clearfog.dts
@@ -152,7 +152,7 @@
compatible = "spidev";
reg = <3>;
spi-max-frequency = <12000000>;
- spi-cpol;
+ // NOTE: the HW appears to have troubles with CPOL=1 toggling -> let's use a physical invertor
linux,spi-wdelay = /bits/ 16 <3>;
};
};