clearfog: Enable MAX14830 quad UART

I had to be very careful when it came to clock naming; simply using
"oscillator" actually mangled the "refclk" on the SoC, which had a nice
side effect of confusing the watchdog timer. Sweet times.

Another funny point were the interrupts. The Mikrobus INT line is
actually pulled *down* by the SoC. The only accessible GPIOs with a
pull-up are J18 (unpopulated) and the UART's TX. Let's just reconfigure
MPP25 (formerly UART TX) for interrupts; this involves the pinctrl
dance, too.

Change-Id: I8a0adb3d15586797ffe6d95fda2365df87ba9e36
diff --git a/board/czechlight/clearfog/czechlight-clearfog.dts b/board/czechlight/clearfog/czechlight-clearfog.dts
index 9a4c0e5..83fb83b 100644
--- a/board/czechlight/clearfog/czechlight-clearfog.dts
+++ b/board/czechlight/clearfog/czechlight-clearfog.dts
@@ -3,3 +3,54 @@
 &w25q32 {
 	status = "okay";
 };
+
+/ {
+	clocks {
+		spi_uart_clk: osc_max14830 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <3686400>;
+		};
+	};
+};
+
+&uart1_pins {
+        status = "disabled";
+};
+
+&uart1 {
+        status = "disabled";
+};
+
+&pinctrl {
+        hack_pins: hack_pins {
+                marvell,pins = "mpp25";
+                marvell,function = "gpio";
+        };
+};
+
+&gpio0 {
+	mikrobus_uart_tx {
+		gpio-hog;
+		/* Mark this as "active high", i.e. "1 is 1", so that the interrupts act on the falling edge */
+		gpios = <25 GPIO_ACTIVE_HIGH>;
+		input;
+		line-name = "SPI-int";
+	};
+};
+
+&spi1 {
+	max14830: max14830@2 {
+		compatible = "maxim,max14830";
+		reg = <2>;
+		clocks = <&spi_uart_clk>;
+		clock-names = "xtal";
+		interrupt-parent = <&gpio0>;
+		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&hack_pins>;
+		pinctrl-names = "default";
+		gpio-controller;
+		#gpio-cells = <2>;
+		spi-max-frequency = <26000000>;
+	};
+};